©2001 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX27 Rev. 1.3.0 8
74LCX27 — Low Voltage Triple 3-Input NOR Gate with 5V Tolerant Inputs
Physical Dimensions
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
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LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14
B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00
4.00
3.80
(0.33)
1.27
0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
