AD7171BCPZ-500RL7 Datasheet AD7171BCPZ-REEL7, AD7171BCPZ-500RL7 | P4-P6

Data Sheet AD7171

Rev. C | Page 3 of 16

SPECIFICATIONS

V

DD

= 2.7 V to 5.25 V, V

REF

= V

DD

, GND = 0 V, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter

AD7171B

1

Unit Test Conditions/Comments

Min Typ Max

ADC CHANNEL

Output Data Rate (f

ADC

) 125 Hz Settling time = 3/f

ADC

No Missing Codes

2

16 Bits

Resolution Peak-to-Peak (p-p) 16 Bits V

INx

= 0 V, V

REF

= V

DD

Effective Resolution (ENOB) 16 Bits V

INx

= 0 V, V

REF

= V

DD

RMS Noise See Table 7 µV V

INx

= 0 V, V

REF

= V

DD

Integral Nonlinearity ±0.4 LSB

Offset Error ±200 μV

Offset Error Drift vs. Temperature ±250 nV/°C

Full-Scale Error ±0.015 % of FS

Gain Drift vs. Temperature

±0.07

LSB/°C

Power Supply Rejection 85 dB V

INx

= 1 V

ANALOG INPUTS

Differential Input Voltage Range

±V

REF

V

REF

= REFIN(+) − REFIN(−)

Absolute AINx Voltage Limits

2

GND − 0.03 V

DD

+ 0.03 V

Average Input Current

2

±400 nA/V Input current varies with input voltage

Average Input Current Drift ±60 pA/V/°C

DC Common-Mode Rejection 90 dB V

INx

= 1 V

REFERENCE

External REFIN Voltage V

DD

V REFIN = REFIN(+) − REFIN(−)

Reference Voltage Range

2

0.5 V

DD

V

Absolute REFIN Voltage Limits

2

GND − 0.03

V

DD

+ 0.03

V

Average Reference Input Current 400 nA/V

Average Reference Input Current Drift ±0.15 nA/V/°C

DC Common-Mode Rejection 110 dB

INTERNAL CLOCK

Frequency

2

64 − 5% 64 + 5% kHz

LOGIC INPUTS

SCLK, PDRST

2

Input Low Voltage, V

INL

0.4 V V

DD

= 3 V

0.8 V V

DD

= 5 V

Input High Voltage, V

INH

1.8 V V

DD

= 3 V

2.4 V V

DD

= 5 V

SCLK (Schmitt-Triggered Input)

2

Hysteresis 100 mV V

DD

= 3 V

140 mV V

DD

= 5 V

Input Currents ±2 µA V

IN

= V

DD

or GND

Input Capacitance 5 pF All digital inputs

AD7171 Data Sheet

Rev. C | Page 4 of 16

Parameter

AD7171B

1

Unit Test Conditions/Comments

Min Typ Max

LOGIC OUTPUT (DOUT/RDY)

Output High Voltage, V

OH

2

V

DD

− 0.6 V V

DD

= 3 V, I

SOURCE

= 100 µA

4 V V

DD

= 5 V, I

SOURCE

= 200 µA

Output Low Voltage, V

OL

2

0.4 V V

DD

= 3 V, I

SINK

= 100 µA

0.4 V V

DD

= 5 V, I

SINK

= 1.6 mA

Floating-State Leakage Current ±2 µA

Floating-State Output Capacitance 5 pF

Data Output Coding Offset binary

POWER REQUIREMENTS

3

Power Supply Voltage

V

DD

− GND 2.7 5.25 V

Power Supply Currents

I

DD

Current 110 130 µA V

DD

= 3 V

135 150 µA V

DD

= 5 V

I

DD

(Power-Down/Reset Mode) 5 µA

1

Temperature range is −40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Digital inputs equal to V

DD

or GND.

Data Sheet AD7171

Rev. C | Page 5 of 16

TIMING CHARACTERISTICS

V

DD

= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V

DD

, unless otherwise noted.

Table 3.

Parameter

1, 2

Limit at T

MIN

, T

MAX

Unit Test Conditions/Comments

READ

t

1

100 ns min SCLK high pulse width

t

2

100 ns min SCLK low pulse width

t

3

0 ns min SCLK active edge to data valid delay

4

60 ns max V

DD

= 4.75 V to 5.25 V

80

ns max

V

DD

= 2.7 V to 3.6 V

t

4

10 ns min

SCLK inactive edge to DOUT/

RDY high

RESET

t

5

100

ns min

PDRST low pulse width

t

6

25 ms typ

PDRST high to data valid delay

1

Sample tested during initial release to ensure compliance. All input signals are specified with t

R

= t

F

= 5 ns (10% to 90% of V

DD

) and timed from a voltage level of 1.6 V.

2

See Figure 3.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V

OL

or V

OH

limits.

4

SCLK active edge is the falling edge of SCLK.

Timing Diagrams

I

SINK

(1.6mA WITH V

DD

= 5V,

100µA WITH V

DD

= 3V)

I

SOURCE

(200µA WITH V

DD

= 5V,

100µA WITH V

DD

= 3V)

1.6V

TO

OUTPUT

50pF

08417-002

Figure 2. Load Circuit for Timing Characterization

t

3

t

1

t

2

t

4

DOUT/RDY (O)

SCLK (I)

I = INPUT, O = OUTPUT

MSB LSB

08417-003

Figure 3. Read Cycle Timing Diagram

t

5

t

6

PDRST (I)

DOUT/RDY (O)

I = INPUT, O = OUTPUT

08417-004

Figure 4. Resetting the AD7171

AD7171BCPZ-500RL7

AD7171BCPZ-500RL7

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