AD7171BCPZ-REEL7 Datasheet AD7171BCPZ-REEL7, AD7171BCPZ-500RL7 | P10-P12

Data Sheet AD7171

Rev. C | Page 9 of 16

OUTPUT NOISE AND RESOLUTION SPECIFICATIONS

Table 7 shows the rms noise of the AD7171. The numbers

given are for a 5 V and a 3 V reference. These numbers are

typical and are generated with a differential input v o lt a g e of 0 V.

The corresponding p-p resolution is also listed along with the

effective resolution (ENOB). Note that the effective resolution is

calculated using the rms noise, whereas the p-p resolution is based

on the p-p noise. The p-p resolution represents the resolution

for which there is no code flicker. These numbers are typical.

The effective number of bits (ENOB) is defined as

ENOB = ln(FSR/RMS noise)/ln(2)

The noise-free bits, or p-p resolution, are defined as

Noise-Free Bits = ln(FSR/Peak-to-Peak Noise)/ln(2)

where FSR is the full-scale range and is equal to 2 × V

REF

/gain.

Table 7. RMS Noise and Resolution of the AD7171

REF

= V

RMS Noise P-P Noise P-P Resolution ENOB

5 V 11.5 μV 76 μV 16 bits 16 bits

3 V 6.9 μV 45 μV 16 bits 16 bits

AD7171 Data Sheet

Rev. C | Page 10 of 16

ADC CIRCUIT INFORMATION

OVERVIEW

The AD7171 is a low power ADC that incorporates a precision

16-bit Σ-∆ modulator and an on-chip digital filter intended for

measuring wide dynamic range, low frequency signals. The device

has an internal clock and one differential input. It operates with

an output data rate of 125 Hz and has a gain of 1. A 2-wire interface

simplifies data retrieval from the AD7171.

FILTER, DATA RATE, AND SETTLING TIME

The AD7171 uses a sinc

filter. The output data rate is set to 125 Hz;

thus, valid conversions are available every 1/125 = 8 ms. If a reset

occurs, then the user must allow the complete settling time for

the first conversion after the reset. The settling time is equal to

24 ms. Subsequent conversions are available at 125 Hz.

When a step change occurs on the analog input, the AD7171

requires several conversion cycles to generate a valid conversion.

If the step change occurs synchronous to the conversion period,

then the settling time of the AD7171 must be allowed to generate

a valid conversion. If the step change occurs asynchronous to the

end of a conversion, then an extra conversion must be allowed to

generate a valid conversion. The data register is updated with all

the conversions but, for an accurate result, the user must allow

the required time.

Figure 12 shows the filter response of the filter. The only external

filtering required on the analog inputs is a simple RC filter to

provide rejection at multiples of the master clock. See Table 8

for suitable external RC combinations.

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 750625500375250125

FILTER GAIN (dB)

INPUT SIGNAL FREQUENCY (Hz)

08417-011

Figure 12. Filter Response

GAIN

The AD7171 has a gain of 1. The acceptable analog input range

is ±V

REF

. Therefore, with V

REF

= 5 V, the input range is ±5 V.

POWER-DOWN/RESET (PDRST)

The

PDRST

pin functions as a power-down pin and a reset pin.

When

PDRST

is taken low, the AD7171 is powered down. The

entire ADC is powered down (including the on-chip clock), and

the DOUT/

RDY

pin is tristated. The circuitry and serial interface

are also reset. This resets the logic, the digital filter, and the analog

modulator.

PDRST

must be held low for 100 ns minimum to

initiate the reset function (see

Figure 4).

When

PDRST

is taken high, the AD7171 is taken out of power-

down mode. When the on-chip clock has powered up (1 ms,

typically), the modulator then begins sampling the analog input.

The DOUT/

RDY

pin becomes active, going high until a valid

conversion is available. A reset is automatically performed on

power-up.

ANALOG INPUT CHANNEL

The AD7171 has one differential analog input channel that is

connected to the modulator; that is, the input is unbuffered.

Note that this unbuffered input path provides a dynamic load to

the driving source. Therefore, resistor/capacitor combinations on

the input pins can cause dc gain errors, depending on the output

impedance of the source that is driving the ADC input. Table 8

shows the allowable external resistance/capacitance values such

that no gain error at the 16-bit level is introduced.

Table 8. External RC Combination for No Gain Error

C (pF)

R (Ω)

50 9000

100 6000

500 1500

1000 900

5000 200

The absolute input voltage range is restricted to a range between

GND − 30 mV and V

+ 30 mV. Care must be taken in setting

up the common-mode voltage to avoid exceeding these limits.

Otherwise, there is degradation in linearity and noise performance.

BIPOLAR CONFIGURATION

The AD7171 accepts a bipolar input range. A bipolar input range

does not imply that the device can tolerate negative voltages with

respect to system GND. Signals on the AIN(+) input are referenced

to the voltage on the AIN(−) input. For example, if AIN(−) is 2.5 V,

the analog input range on the AIN(+) input is 0 V to 5 V when a

2.5 V reference is used.

Data Sheet AD7171

Rev. C | Page 11 of 16

DATA OUTPUT CODING

The AD7171 uses offset binary coding. Therefore, a negative

full-scale voltage results in a code of 000...000, a zero differential

input voltage results in a code of 100...000, and a positive full-

scale input voltage results in a code of 111...111. The output

code for any analog input voltage can be represented as

Code = 2

N – 1

× ((V

INx

REF

) + 1)

where:

INx

is the analog input voltage.

N = 16 for the AD7171.

REFERENCE

The AD7171 has a fully differential input capability for the channel.

The common-mode range for these differential inputs is GND to

. The reference input is unbuffered; therefore, excessive RC

source impedances introduce gain errors. The reference voltage

REFIN (REFIN(+) − REFIN(−)) is V

nominal, but the AD7171

is functional with reference voltages of 0.5 V to V

. In applications

where the excitation (voltage or current) for the transducer on

the analog input also drives the reference voltage for the device,

the effect of the low frequency noise in the excitation source is

removed because the application is ratiometric. If the AD7171 is

used in a nonratiometric application, a low noise reference

should be used.

Recommended 2.5 V reference voltage sources for the AD7171

include the ADR381 and ADR391, which are low noise, low

power references. Also, note that the reference inputs provide a

high impedance, dynamic load. Because the input impedance of

each reference input is dynamic, resistor/capacitor combinations

on these inputs can cause dc gain errors, depending on the output

impedance of the source that is driving the reference inputs.

Reference voltage sources such as those recommended above

(the ADR391, for example) typically have low output impedances

and are, therefore, tolerant to decoupling capacitors on REFIN(+)

without introducing gain errors in the system. Deriving the

reference input voltage across an external resistor means that

the reference input sees a significant external source impedance.

External decoupling on the REFIN(±) pins is not recommended

in this type of circuit configuration.

DIGITAL INTERFACE

The serial interface of the AD7171 consists of two signals: SCLK

and DOUT/

RDY

SCLK is the serial clock input for the device,

and data transfers occur with respect to the SCLK signal. The

DOUT/

RDY

pin is dual purpose: it functions as a data ready

pin and as a data out pin. DOUT/

RDY

goes low when a new

data-word is available in the output register. A 24-bit word is

placed on the DOUT/

RDY

pin when sufficient SCLK pulses are

applied. This consists of a 16-bit conversion result followed by

eight status bits.

Table 9 shows the functions of the status bits.

RDY

: Ready bit. This bit is set low to indicate that a conversion

is available.

0: This bit is set to 0.

ERR: This bit is set to 1 if an error occurred during the conversion.

An error occurs when the analog input is outside range.

ID1, ID0: ID bits. These bits indicate the ID number for the

AD7171. Bit ID1 is set to 0 and Bit ID0 is set to 1 for the AD7171.

PAT2, PAT1, PAT0: Status pattern bits. These bits are set to 101

by default. When the user reads the data from the AD7171, a

pattern check can be performed. If the PAT2 to PAT0 bits are

different from their default values, the serial transfer from the

ADC was not performed correctly.

Table 9. Status Bits

RDY

0 ERR ID1 ID0 PAT2 PAT1 PAT0

DOUT/

RDY

is reset high when the conversion is read. If the

conversion is not read, DOUT/

RDY

goes high prior to the data

ensures that a read operation is not attempted while the register

is being updated. Each conversion can be read only once. The

data register is updated for every conversion. Therefore, when a

conversion is complete, the serial interface resets, and the new

conversion is placed in the data register. Therefore, the user

must ensure that the complete word is read before the next

conversion is complete.

When

PDRST

is low, the DOUT/

RDY

pin is tristated. When

PDRST

is taken high, the internal clock requires 1 ms, approx-

imately, to power up. Following this, the ADC continuously

converts. The first conversion requires the complete settling

time (see Figure 4). DOUT/

RDY

goes high when

PDRST

taken high and returns low only when a conversion is available.

The ADC then converts continuously, subsequent conversions

being available at 125 Hz.

Figure 3 shows the timing for a read

operation from the AD7171.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7171BCPZ-REEL7

Mfr. #:

Buy AD7171BCPZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 1CH L/POWER 16-BIT SD GAIN 128 IC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7171BCPZ-REEL7

AD7171BCPZ-REEL7

Products related to this Datasheet