5/21/2012 - 1 - www.onsemi.com
Test Procedure for the NV47711PDAJGEVB Evaluation Board
Test Procedure:
1. Connect the test setup as is shown in Figure 1. See Table 1 with required equipment.
- Letter F – Force line
- Letter S – Sense line
2. Select output current limit by connecting jumper J
5
– J
8
.
- J
5
– I
LIM0
~ 10 mA
- J
6
– I
LIM1
~ 170 mA
- J
7
– I
LIM2
~ 340 mA
- J
8
– I
LIM3
– R
CSO3
position available for individual current limit setting by resistor from
range 728 Ω to 25.5 kΩ
3. Set Input Voltage and turn on Power Supply.
4. Enable chip by connecting external Voltage Source on jumper J
3
. Output voltage must be higher
than 2.31 V but maximally 7 V.
5. Set load current (max 350 mA) and turn on Load.
6. Monitor Output voltage, it’s given according to Equation 1.
(eq. 1)
7. Monitor CSO voltage on connector J
4
. It should be max 2.55 V in steady state. The CSO voltage
is proportional to output current according to Equation 2.
(eq. 2)
8. Compare your results with measured results in Table 2.
