13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
AC ELECTRICAL CHARACTERISTICS ASYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Commercial Com’l & Ind’l
(2)
Commercial Commercial
IDT72T1845L4-4 IDT72T1845L5 IDT72T1845L6-7
IDT72T1855L4-4 IDT72T1855L5 IDT72T1855L6-7
IDT72T1865L4-4 IDT72T1865L5 IDT72T1865L6-7
IDT72T1875L4-4 IDT72T1875L5 IDT72T1875L6-7
IDT72T1885L4-4 IDT72T1885L5 IDT72T1885L6-7
IDT72T1895L4-4 IDT72T1895L5 IDT72T1895L6-7
IDT72T18105L4-4 IDT72T18105L5 IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L4-4 IDT72T18115L5 IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L4-4 IDT72T18125L5 IDT72T18125L6-7 IDT72T18125L10
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fA Cycle Frequency (Asynchronous) 100 83 66 50 MHz
tAA Data Access Time 0.6 8 0.6 10 0.6 12 0.6 14 ns
tCYC Cycle Time 10 12 15 20 ns
tCYH Cycle HIGH Time 4.5 5 7 8 ns
tCYL Cycle LOW Time 4.5 5 7 8 ns
tRPE Read Pulse after EF HIGH 8 10 12 14 ns
tFFA Clock to Asynchronous FF 8 10—12—14ns
tEFA Clock to Asynchronous EF 8 10—12—14ns
tPAFA Clock to Asynchronous Programmable Almost-Full Flag 8 10 12 14 ns
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag 8 10 12 14 ns
tOLZ Output Enable to Output in Low Z
(3)
0—0—00ns
tOE Output Enable to Output Valid 3.4 3.6 3.8 4.5 ns
tOHZ Output Enable to Output in High Z
(3)
3.4 3.6 3.8 4.5 ns
tHF Clock to HF 8 10—12—14ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Values guaranteed by design, not currently tested.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Input Pulse Levels 0.25 to 1.25V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.75
Output Reference Levels V
DDQ/2
HSTL
1.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
AC TEST LOADS
Figure 2a. AC Test Load
Input Pulse Levels 0.4 to 1.4V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.9
Output Reference Levels V
DDQ/2
EXTENDED HSTL
1.8V AC TEST CONDITIONS
Input Pulse Levels GND to 2.5V
Input Rise/Fall Times 1ns
Input Timing Reference Levels VCC/2
Output Reference Levels V
DDQ/2
2.5V LVTTL
2.5V AC TEST CONDITIONS
5909 drw04
50
V
DDQ
/2
I/O
Z
0
= 50
5909 drw04a
6
5
4
3
2
1
20 30 50 80 100 200
Capacitance (pF)
tCD
(Typical, ns)
NOTE:
1. VDDQ = 1.5V±.
NOTE:
1. VDDQ = 1.8V±.
NOTE:
1. For LVTTL VCC = VDDQ.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
OUTPUT ENABLE & DISABLE TIMING
V
IH
OE
V
IL
tOE & tOLZ
VCC
2
VCC
2
100mV
100mV
tOHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
VCC
2
VCC
2
5909 drw04b
Output
Enable
Output
Disable
READ CHIP SELECT ENABLE & DISABLE TIMING
V
IH
RCS
V
IL
tENS
tENH
tRCSLZ
RCLK
VCC
2
VCC
2
100mV
100mV
tRCSHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
VCC
2
5909 drw04c
NOTES:
1. REN is HIGH.
2. RCS is LOW.
NOTES:
1. REN is HIGH.
2. OE is LOW.

72T1895L5BBI8

Mfr. #:
Manufacturer:
Description:
IC FIFO 65536X18 5NS 144BGA
Lifecycle:
New from this manufacturer.
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