IDT82V3396 SHORT FORM DATASHEET DUAL SYNCHRONOUS ETHERNET LINE CARD PLL
Pin Description 5 February 4, 2013
2 PIN DESCRIPTION
Table 1: Pin Description
Name Pin No. I/O Type
Description
1, 2
Global Control Signal
OSCI 6 I CMOS
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
SONET/SDH 72
I
pull-down
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST 55
I
pull-up
CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1 33
I
pull-down
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2 38
I
pull-down
CMOS
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
IN1_POS
IN1_NEG
29
30
I PECL/LVDS
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
or 156.25 MHz is differentially input on this pair of pins. Whether the clock signal is PECL or
LVDS is automatically detected.
Single-ended input for differential input is also supported.
IN2_POS
IN2_NEG
31
32
I PECL/LVDS
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A 2kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
or 156.25 MHz clock is differentially input on this pair of pins. Whether the clock signal is
PECL or LVDS is automatically detected.
Single-ended input for differential input is also supported.
IN3 34
I
pull-down
CMOS
IN3: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
IN4 35
I
pull-down
CMOS
IN4: Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
IN5 39
I
pull-down
CMOS
IN5: Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
IN6 40
I
pull-down
CMOS
IN6: Input Clock 6
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
Output Frame Synchronization Signal
FRSYN-
C_8K_1PPS
19 O CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
