PmodALS™ Reference Manual
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2 Interfacing with the Pmod
The PmodALS communicates with the host board via the SPI protocol. Since the on-board analog-to-digital
converter is a read-only module, the only wires in the SPI protocol that are required are the Chip Select, Master-In-
Slave-Out, and Serial Clock lines. The location of each of these lines on the Pmod header are shown in the table
below.
2.1 Pinout Description Table
Table 1. Connector J1: Pin descriptions as labeled on the Pmod.
The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin
low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK to be
between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on the
subsequent rising edge of SCLK, consist of three leading zeroes, the eight bits of information with the MSB first,
and four trailing zeroes.
Any external power applied to the PmodALS must be within 2.7V and 5.25V; however, it is recommended that
Pmod is operated at 3.3V.
3 Physical Dimensions
The pins on the pin header are spaced 100 mil apart. The PCB is 0.8 inches long on the sides parallel to the pins on
the pin header and 0.8 inches long on the sides perpendicular to the pin header.
