6.42
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
13
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'.
5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'.
6. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
7024X15
Com'l Only
7024X17
Com'l Only
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
15
____
17
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Match
____
15
____
17
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
15
____
17
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
15
____
17
____
17
____
17 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
18
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5 )
12
____
13
____
15
____
17
____
ns
BUSY INPUT TIMING (M/S = V
IH
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
12
____
13
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
30
____
30
____
45
____
50 ns
t
DDD
Write Data Valid to Read Data Delay
(1 )
____
25
____
25
____
35
____
35 ns
2740 tbl 14a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
45
____
45 ns
t
BDA
BUSY Disable Time from Address Not Match
____
20
____
40
____
40 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
20
____
40
____
40 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
20
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
35
____
40
____
45 ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
25
____
ns
BUSY INPUT TIMING (M/S = V
IH
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80
____
95 ns
t
DDD
Write Data Valid to Read Data Delay
(1 )
____
45
____
65
____
80 ns
2740 tbl 14b
