AD8055/AD8056
Rev. J | Page 13 of 16
FREQUENCY (MHz)
5
4
–5
1
–2
–3
–4
3
2
–1
0
NORMALIZED GAIN (dB)
0.3 1 10 100 500
C
L
402
100
402
50
V
IN
=0dBm
C
L
=0pF
C
L
= 10pF
C
L
= 20pF
C
L
=30pF
01063-039
POWER DISSIPATION LIMITS
With a 10 V supply (total V
CC
− V
EE
), the quiescent power
dissipation of the AD8055 in the SOT-23-5 package is 65 mW,
while the quiescent power dissipation of the AD8056 in the
MSOP-8 is 120 mW. This translates into a 15.6°C rise above the
ambient for the SOT-23-5 package and a 24°C rise for the
MSOP-8 package.
The power dissipated under heavy load conditions is
approximately equal to the supply voltage minus the output
voltage, times the load current, plus the quiescent power
previously computed. The total power dissipation is then
multiplied by the thermal resistance of the package to find the
temperature rise, above ambient, of the part. The junction
temperature should be kept below 150°C.
Figure 39. Capacitive Load Drive
In general, to minimize peaking or to ensure the stability for
larger values of capacitive loads, a small series resistor, R
The AD8055 in the SOT-23-5 package can dissipate 270 mW,
while the AD8056 in the MSOP-8 package can dissipate
325 mW (at 85°C ambient) without exceeding the maximum
die temperature. In the case of the AD8056, this is greater than
1.5 V rms into 50 Ω, enough to accommodate a 4 V p-p sine
wave signal on both outputs simultaneously. However, because
each output of the AD8055 or AD8056 is capable of supplying
as much as 110 mA into a short circuit, a continuous short-
circuit condition will exceed the maximum safe junction
temperature.
S
, can
be added between the op amp output and the capacitor, C
L
. For
the setup depicted in
Figure 40, the relationship between R
S
and
C
RESISTOR SELECTION
Table 3 is a guide for resistor selection for maintaining gain
flatness vs. frequency for various values of gain.
Table 3.
Gain R
F
(Ω) R
G
(Ω) −3 dB Bandwidth (MHz)
+1 0 300
+2 402 402 160
+5 1 k 249 45
+10 909 100 20
DRIVING CAPACITIVE LOADS
When driving a capacitive load, most op amps exhibit peaking
in the frequency response just before the frequency rolls off.
Figure 39 shows the responses for an AD8056 running at a gain
of +2, with an 100 Ω load that is shunted by various values of
capacitance. It can be seen that under these conditions the part
is still stable with capacitive loads of up to 30 pF.
L
was empirically derived and is shown in Figure 41. R
S
was
chosen to produce less than 1 dB of peaking in the frequency
response. Note also that after a sharp rise, R
S
quickly settles to
approximately 25 Ω.
50
AD8055
+5V
–5V
402
402
6
7
2
3
4
FET PROBE
V
IN
=0dBm
V
OUT
R
S
C
L
0.1µF 10µF
0.1µF 10µF
01063-040
Figure 40. Setup for R
vs. C
S L
40
0
35
20
15
10
5
30
25
C
L
(pF)
R
S
()
0 102030405060270
01063-041
Figure 41. R
vs. C
S L
AD8055/AD8056
Rev. J | Page 14 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001-BA
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210
(5.33)
MAX
PIN 1
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
1
4
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 42. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
AD8055/AD8056
Rev. J | Page 15 of 16
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
PIN 1
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
5
123
4
0.22
0.08
10°
0.50
0.30
0.15 MAX
SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 45. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters

AD8056ARM

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers SGL 300MHz VTG Feedback
Lifecycle:
New from this manufacturer.
Delivery:
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