REVISION B 10/15/15 9 FEMTOCLOCK
®
CRYSTAL-TO-LVDS 150MHZ CLOCK GENERATOR
844244I-04 DATA SHEET
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844244I-04 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD
and V
DDA
should be individually connected
to the power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates this for a
generic V
DD
pin and also shows that V
DDA
requires that an additional
10 resistor along with a 10F bypass capacitor be connected to the
V
DDA
pin.
Figure 1. Power Supply Filtering
Crystal Input Interface
The 844244I-04 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
V
DD
V
DDA
3.3V or 2.5V
10
Ω
10µF.01µF
.01µF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
