© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 6
1 Publication Order Number:
NB3N108K/D
NB3N108K
3.3V Differential 1:8 Fanout
Clock Data Driver with
HCSL Outputs
Description
The NB3N108K is a differential 1:8 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N108K is designed
with HCSL PCI Express clock distribution and FBDIMM
applications in mind.
Inputs can directly accept differential LVPECL, LVDS, HCSL
signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external V
th
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from IREF
(Pin 1) to GND per Figure 6. Outputs can also interface to LVDS
receivers when terminated per Figure 11.
The NB3N108K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB3N108K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequency 100, 133, 166, or 400 MHz
• 220 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each Diff
Pair
• 0.1 ps Typical Integrated Phase Jitter RMS
• Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
• Differential HCSL Output Levels
• LVDS Output Levels with Interface Termination
• These are Pb−Free Devices
Applications
• Clock Distribution
• PCIe I, II, III
• Networking and Communications
• High End Computing
• Routers
End Products
• Servers
• FBDIMM Memory Card
• Ethernet Switch/Routers
*For additional marking information, refer to
Application Note AND8002/D.
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
http://onsemi.com
Figure 1. Simplified Logic Diagram
Q0
Q0
Q1
Q1
Q6
Q6
Q7
Q7
CLK
CLK
V
CC
GND
R
REF
IREF
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
VTCLK
VTCLK
32
1
NB3N
108K
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
