NB3N108KMNR4G

NB3N108K
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4
Table 4. DC CHARACTERISTICS (V
CC
= 3.0 V to 3.6 V, T
A
= 40°C to +85°C Note 4)
Symbol
Characteristic Min Typ Max Unit
I
GND
GND Supply Current (All Outputs Loaded) 60 90 mA
I
CC
Power Supply Current (All Outputs Loaded) 190 230 mA
I
IH
Input HIGH Current 2.0 150
mA
I
IL
Input LOW Current 150 2.0
mA
R
TIN
Internal Input Termination Resistor 45 50 55
W
DIFFERENTIAL INPUT DRIVEN SINGLEENDED
V
th
Input Threshold Reference Voltage Range (Note 5) 350 V
CC
1000 mV
V
IH
Single*Ended Input HIGH Voltage V
th
+ 150 V
CC
mV
V
IL
Single*Ended Input LOW Voltage GND V
th
150 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8 and 9)
V
IHD
Differential Input HIGH Voltage 425 V
CC
850 mV
V
ILD
Differential Input LOW Voltage GND V
CC
1000 mV
V
ID
Differential Input Voltage (V
IHD
* V
ILD
) 150 V
CC
850 mV
V
CMR
Input Common Mode Range 350 V
CC
1000 mV
HCSL OUTPUTS (Figure 4)
V
OH
Output HIGH Voltage 600 740 900 mV
V
OL
Output LOW Voltage 150 0 150 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurements taken with with outputs loaded 50 W to GND, see Figure 6. Connect a 475 W resistor from IREF (Pin 1) to GND per Figure 6.
5. V
th
is applied to the complementary input when operating in single ended mode per Figure 4.
NB3N108K
http://onsemi.com
5
Table 5. AC CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, GND = 0 V; 40°C to +85°C (Note 6)
Symbol
Characteristic Min Typ Max Unit
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
) f
in
400 MHz 725 1000 mV
t
PLH
,
t
PHL
Propagation Delay (See Figure 3a) CLK/CLK to Qx/Qx 550 800 1100 ps
Dt
PLH
,
Dt
PHL
Propagation Delay Variation Per Each Diff Pair
(Note 7) (See Figure 3a) CLK/CLK to Qx/Qx 100
ps
t
SKEW
Duty Cycle Skew (Note 8)
Within Device Skew
Device to Device Skew (Note 9)
20
100
150
ps
t
JIT
f
Integrated Phase Jitter RMS (Note 10) 0.1 ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration)
0.150 V
CC
0.85
V
V
CROSS
Absolute Crossing Magnitude Voltage (See Figure 3b) 250 550 mV
DV
CROSS
Variation in Magnitude of V
CROSS
(See Figure 3b) 150 mV
t
r
, t
f
Absolute Magnitude in Output Risetime and Falltime (from 175 mV to 525 mV)
(See Figure 3b) Qx, Qx 150 220 400
ps
Dtr, Dtf
Variation in Magnitude of Risetime and Falltime (SingleEnded) (See Figure 3b) Qx, Qx 125 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Measured by forcing V
INPP
(MIN) from a 50% duty cycle. Measurement taken with all outputs loaded 50 W to GND per Figure 6. Connect
a 475 W resistor from IREF (Pin 1) to GND per Figure 6.
7. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per Figure 3.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw
and T
pw+
.
9. Skew is measured between outputs under identical transition conditions @ 50 MHz.
10.Phase noise integrated from 12 kHz to 20 MHz.
Figure 3. AC Reference Measurement
CLK
CLK
Q
Q
t
P
LH t
P
HL
V
INPP
= V
IH
(CLK) V
IL
(CLK)
= V
IH
(CLK) V
IL
(CLK)
V
OUTPP
= V
OH
(Q
x
) V
OL
(Q
x
)
= V
OH
(Q
x
) V
OL
(Q
x
)
Dt
P
LH Dt
P
HL
t
r
t
f
525 mV
175 mV
525 mV
175 mV
DV
CROSS
V
CROSS
tr
MAX
tr
MIN
= Dt
r
tr
MIN
tf
MAX
tf
MIN
= Dt
f
tf
MIN
tf
MAX
tr
MAX
(a) Propagation Delay and
Propagation Delay Variation
(b) tr, tf and Dtr, Dtf
(c) VCROSS and DVCROSS
Q
x
Q
x
Q
x
Q
x
Q
x
Q
x
NB3N108K
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6
Figure 4. SingleEnded Interconnect V
th
Reference
Voltage
CLK
V
th
CLK
V
th
V
CC
V
EE
V
CMRmin
V
CMRmax
V
CMR
IN
IN
V
IHDmax
V
ILDmax
V
ID
= V
IHD
V
ILD
V
IHDtyp
V
ILDtyp
V
IHDmin
V
ILDmin
Figure 5. V
th
Diagram
Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation
A. Connect 475 W resistor RREF from IREF pin to GND.
B. R
S1
, R
S2
: 0 W for Test and Evaluation. Select to Minimizing Ringing.
C. C
L1
, C
L2
: Receiver Input Simulation (for test only not added to application circuit.
D. D
L1
, D
L2
Termination and Load Resistors Located at Received Inputs.
C
L1
C
2 pF
C
L2
C
2 pF
Z
0
= 50 W
Z
0
= 50 W
Receiver
R
S1
B
R
S2
B
NB3N108K
HCSL
Driver
R
REF
A
R
L1
D
50 W
R
L2
D
50 W
Qx
Qx
IREF
50 W*
V
TCLK
= V
TCLK
= V
CC
2.0 V
LVPECL
Driver
Z
0
= 50 W
Z
0
= 50 W
V
CC
= 3.3 V / 2.5 V V
CC
= 3.3 V
GND GND
50 W*
V
TCLK
V
TCLK
Figure 7. LVPECL Interface
*RTIN, Internal Input Termination Resistor
50 W*
V
TCLK
= V
TCLK
LVDS
Driver
Z
0
= 50 W
Z
0
= 50 W
V
CC
= 3.3 V / 2.5 V / 1.8 V V
CC
= 3.3 V
GND GND
50 W*
V
TCLK
V
TCLK
CLK
Figure 8. LVDS Interface
*RTIN, Internal Input Termination Resistor
NB3N108K NB3N108K
CLK
CLK
CLK

NB3N108KMNR4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:8 HCSL FAN-OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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