Rev A 7/10/15 7 LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
8536-02 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to
the power value of the fundamental. This ratio is expressed in
decibels (dBm) or a ratio of the power in the 1Hz band to the power
in the fundamental. When the required offset is specified, the phase
noise is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "SMA 100 Generator 9kHz – 6GHz as
external input to an Agilent 8133A 3HGz Pulse Generator”.
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.149ps (typical)
LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
8 Rev A 7/10/15
8536-02 DATA SHEET
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Propagation Delay
2.5V LVPECL Output Load AC Test Circuit
Output Skew
Output Duty Cycle/Pulse Width/Period
SCOPE
Qx
nQx
V
EE
tsk(pp)
Part 1
Part 2
t
PD
V
CC
2
SCOPE
Qx
nQx
V
EE
Rev A 7/10/15 9 LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
8536-02 DATA SHEET
Parameter Measurement Information, continued
Output Rise/Fall Time MUX_ISOLATION
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
CLK0 Input
For applications not requiring the use of the clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK0 input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVPECL Outputs
The unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Amplitude (dB)
A0
Spectrum of Output Signal Q
MUX
_ISOL
= A0 – A1
(fundamental)
Frequency
ƒ
MUX selects static input
MUX selects active
input clock signal
A1

8536AG-02LFT

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution 6 LVPECL OUT BUFFER
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New from this manufacturer.
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