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CY2VC511ZXC

P1-P3P4-P6P7-P7
PRELIMINARY
CY2VC511
Document Number: 001-10796 Rev. *D Page 4 of 7
Parameter Measurements
Figure 2. Output Duty Cycle Timing
Figure 3. Output Rise and Fall Time
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
I
DD
Operating Supply Current V
DD
= 3.465V, output unloaded – – 110 mA
V
OH
High Output Voltage V
DD
= min, I
OH
= –4 mA 0.9*V
DD
–– V
V
OL
Low Output Voltage V
DD
= max, I
OL
= 4 mA – – 0.1*V
DD
V
V
IH
Input High Voltage For REFIN 1.25 – 1.8 V
V
IL
Input Low Voltage For REFIN – – 0.25 V
V
VIN
VIN Input Voltage 0 – V
DD
V
I
VIN
VIN Input Current V
SS
≤ VIN
≤ V
DD
–10 – 60 μA
INL
VIN
[3, 4]
VIN to F
OUT
Integral Nonlin-
earity
V
SS
≤ VIN
≤ V
DD
–1–%
AC Electrical Characteristics
[3]
Parameter Description Test Conditions Min Typ Max Unit
F
OUT
Output Frequency – 27 – MHz
PR Pull Range VIN = V
DD
to V
SS
, relative to nominal f
OUT
(VIN = 1.65V) across operating temperature and
supply voltage.
±115 – – ppm
T
DC
Duty Cycle Measured at V
DD
/2, defined in Figure 2 45 50 55 %
T
R
Output Rise Time 20% to 80% of V
DD
, C
LOAD
= 15 pF – 0.7 1.5 ns
T
F
Output Fall Time 80% to 20% of V
DD
, C
LOAD
= 15 pF – 0.8 1.5 ns
T
LOCK
Start Up Time Time for CLK to reach valid frequency measured
from the time V
DD
= V
DD
(min)
––5ms
Note
3. Not 100% tested, guaranteed by design and characterization.
4. Integral nonlinearity is defined in IEEE Standard 1241-2000.
CLK
20%
80%
T
R
T
F
20%
80%
V
DD
0V
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PRELIMINARY
CY2VC511
Document Number: 001-10796 Rev. *D Page 5 of 7
Package Drawings and Dimensions
Figure 4. 16-Pin TSSOP 4.40 mm Body
Ordering Information
Part Number Package Description Product Flow
Pb-Free
CY2VC511ZXC 16-Pin TSSOP Commercial, 0° to 70°C
CY2VC511ZXCT 16-Pin TSSOP - Tape and Reel Commercial, 0° to 70°C
51-85091 *B
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PRELIMINARY
CY2VC511
Document Number: 001-10796 Rev. *D Page 6 of 7
Document History Page
Document Title: CY2VC511 27 MHz Clock Generator with VCXO
Document Number: 001-10796
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 506248 RGL See ECN New data sheet
*A 1285703 JWK/KVM/
ARI
See ECN Changed definition of nominal frequency to VIN = 1.65V
Added C
LOAD
specification
Changed R
UP
value
Corrected T
R
/T
F
conditions and specification
Removed pull down resistor on SEL
Updated several drawings
Edited data sheet for template compliance
*B 2705638 XHT/KVM/
AESA
05/13/2009 Changed title from Low Noise Clock Generator with VCXO to 27 MHz Clock
Generator with VCXO, Basic configuration change: Reference changed from
crystal to driven clock, Output changed from 216 MHz to 27 MHz, Pinout changed
to show no connects, Pin 11 changed to DNU, V
DD
range changed from ±0.2V to
±5%, Thermal resistance data added, IOL & IOH changed from 2mA to 4mA
Phase noise specs removed, IIVIN changed from 10μA to 60μA, Rise & fall times
changed, IDD changed
*C 2768029 KVM 09/18/2009 Remove reference to OE/PD# pin in I
DD
spec
Change parameter name I
IVIN
to I
VIN
Change parameter LIN to INL
VIN
, add note to definition
Add max limit for T
R
, T
F
: 1.5 ns
Change T
LOCK
max from 10 ms to 5 ms
*D 2905106 KVM 05/14/10 Updated package diagram.
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CY2VC511ZXC

Mfr. #:
Buy CY2VC511ZXC
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 27MHz CLK GENERATOR W/VCXO COM
Lifecycle:
New from this manufacturer.
Delivery:
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