AT28LV010-20JU-051

Features
Single 3.3V ± 10% Supply
Fast Read Access Time – 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 128 Bytes
Internal Control Timer
Fast Write Cycle Time
Page Write Cycle Time – 10 ms Maximum
1 to 128-Byte Page Write Operation
Low Power Dissipation
15 mA Active Current
–20 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 10
5
Cycles
Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option Only
1. Description
The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Program-
mable Read-Only Memory. Its 1 megabit of memory is organized as 131,072 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 54 mW. When the device
is deselected, the CMOS standby current is less than 20 µA.
The AT28LV010 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to
128 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA
polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s 28LV010 has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved
data retention characteristics. Software data protection is implemented to guard
against inadvertent writes. The device also includes an extra 128 bytes of EEPROM
for device identification or tracking.
1-Megabit
(128K x 8)
Low Voltage
Paged Parallel
EEPROMs
AT28LV010
0395F–PEEPR–08/09
2
0395F–PEEPR–08/09
AT28LV010
2. Pin Configurations
2.1 32-lead PLCC Top View
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
DC
VCC
WE
NC
2.2 32-lead TSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
3
0395F–PEEPR–08/09
AT28LV010
3. Block Diagram
4. Device Operation
4.1 Read
The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE
or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2 Write
The write operation of the AT28LV010 allows 1 to 128 bytes of data to be written into the
device during a single internal programming period. Each write operation must be preceded by
the software data protection (SDP) command sequence. This sequence is a series of three
unique write command operations that enable the internal write circuitry. The command
sequence and the data to be written must conform to the software protected write cycle timing.
Addresses are latched on the falling edge of WE
or CE, whichever occurs last and data is
latched on the rising edge of WE
or CE, whichever occurs first. Each successive byte must be
written within 150 µs (t
BLC
) of the previous byte. If the t
BLC
limit is exceeded the AT28LV010
will cease accepting data and commence the internal programming operation. If more than
one data byte is to be written during a single programming operation, they must reside on the
same page as defined by the state of the A7 - A16 inputs. For each WE
high to low transition
during the page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.

AT28LV010-20JU-051

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
EEPROM 200NS, PLCC, IND TEMP, GREEN
Lifecycle:
New from this manufacturer.
Delivery:
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