MAX9376EUB+ Datasheet MAX9376EUB+, MAX9376EUB+T | P4-P6

MAX9376

LVDS/Anything-to-LVPECL/LVDS Dual Translator

4 _______________________________________________________________________________________

SUPPLY CURRENT

vs. FREQUENCY

MAX9376 toc01

FREQUENCY (MHz)

SUPPLY CURRENT (mA)

15001000500

02000

LVPECL OUTPUTS

UNLOADED

OUTPUT AMPLITUDE

vs. FREQUENCY

MAX9376 toc02

FREQUENCY (MHz)

OUTPUT AMPLITUDE (mV)

15001000500

400

500

600

700

800

900

300

02000

LVPECL

LVDS

PROPAGATION DELAY

vs. TEMPERATURE

MAX9376 toc03

TEMPERATURE (°C)

PROPAGATION DELAY (ps)

603510-15

320

340

360

380

400

420

440

460

480

500

300

-40 85

PLH

(LVPECL)

PHL

(LVPECL)

PLH

(LVDS)

PHL

(LVDS)

OUTPUT RISE/FALL TIME

vs. TEMPERATURE

MAX9376 toc04

TEMPERATURE (°C)

OUTPUT RISE/FALL TIME (ps)

603510-15

100

110

120

130

140

-40 85

(LVPECL)

(LVDS)

(LVPECL)

Typical Operating Characteristics

= +3.3V, differential input voltage |V

| = 0.2V, V

= 1.2V, input frequency = 500MHz, LVPECL outputs terminated with 50Ω

±1% to V

- 2.0V, LVDS outputs terminated with 100Ω ±1%, T

= +25°C, unless otherwise noted.)

AC ELECTRICAL CHARACTERISTICS (continued)

= +3.0V to +3.6V, differential input voltage |V

| = 0.1V to 1.2V, input frequency ≤ 1.34GHz, differential input transition time =

125ps (20% to 80%), input voltage (V

, V

) = 0 to V

, input common-mode voltage (V

) = 0.05V to (V

- 0.05V), LVPECL out-

puts terminated with 50Ω ±1% to (V

- 2.0V), LVDS outputs terminated with 100Ω ±1%, T

= -40°C to +85°C. Typical values are at

= +3.3V, |V

| = 0.2V, input common-mode voltage V

= 1.2V, T

= +25°C, unless otherwise noted.) (Note 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Added Random Jitter t

= 1.34GHz (Note 7) 0.8 2 ps

(

RMS

)

Note 2: Measurements are made with the device in thermal equilibrium. All voltages are referenced to ground except V

THD

, V

, and ΔV

Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative.

Note 4: DC parameters production tested at T

= +25°C and guaranteed by design and characterization over the full operating

temperature range.

Note 5: Guaranteed by design and characterization, not production tested. Limits are set at ±6 sigma.

Note 6: t

SKEW

is the magnitude difference of differential propagation delays for the same output under same conditions; t

SKEW

PHL

- t

PLH

Note 7: Device jitter added to the input signal.

MAX9376

LVDS/Anything-to-LVPECL/LVDS Dual Translator

_______________________________________________________________________________________ 5

Pin Description

PIN NAME FUNCTION

1 IN1 Differential LVDS/Anything Noninverting Input 1

2 IN1 Differential LVDS/Anything Inverting Input 1

3 OUT2 Differential LVDS Noninverting Output 2. Terminate with 100Ω ±1% to OUT2.

4 OUT2 Differential LVDS Inverting Output 2. Terminate with 100Ω ±1% to OUT2.

5 GND Ground

6 IN2 Differential LVDS/Anything Inverting Input 2

7 IN2 Differential LVDS/Anything Noninverting Input 2

8 OUT1 Differential LVPECL Inverting Output. Terminate with 50Ω ±1% to V

- 2V.

9 OUT1 Differential LVPECL Noninverting Output. Terminate with 50Ω ±1% to V

- 2V.

10 V

Positive Supply. Bypass from V

to GND with 0.1µF and 0.01µF ceramic capacitors. Place

the capacitors as close to the device as possible with the smaller value capacitor closest to

the device.

Detailed Description

The MAX9376 is a fully differential, high-speed,

LVDS/anything-to-LVPECL/LVDS dual translator

designed for signal rates up to 2GHz. One channel is

LVDS/anything-to-LVPECL translator and the other

channel is LVDS/anything-to-LVDS translator. The

MAX9376’s extremely low propagation delay and high

speed make it ideal for various high-speed network

routing and backplane applications.

The MAX9376 accepts any differential input signal with-

in the supply rails and with a minimum amplitude of

100mV. Inputs are fully compatible with the LVDS,

LVPECL, HSTL, and CML differential signaling stan-

dards. LVPECL outputs have sufficient current to drive

50Ω transmission lines. LVDS outputs conform to the

ANSI EIA/TIA-644 LVDS standard.

Inputs

Inputs have a wide common-mode range of 0.05V to

- 0.05V, which accommodates any differential sig-

nals within rails, and requires a minimum of 100mV to

switch the outputs. This allows the MAX9376 inputs to

support virtually any differential signaling standard.

LVPECL Outputs

The MAX9376 LVPECL outputs are emitter followers

that require external resistive paths to a voltage source

= V

- 2.0V typ) more negative than worst-case

for proper static and dynamic operation. When

properly terminated, the outputs generate steady-state

voltage levels, V

or V

with fast transition edges

between state levels. Output current always flows into

the termination during proper operation.

LVDS Outputs

The MAX9376 LVDS outputs require a resistive load to

terminate the signal and complete the transmission

loop. Because the device switches current and not volt-

age, the actual output voltage swing is determined by

the value of the termination resistor. With a 3.5mA typi-

cal output current, the MAX9376 produces an output

voltage of 350mV when driving a 100Ω load.

MAX9376

LVDS/Anything-to-LVPECL/LVDS Dual Translator

6 _______________________________________________________________________________________

Applications Information

LVPECL Output Termination

Terminate the MAX9376 LVPECL outputs with 50Ω to

- 2V) or use equivalent Thevenin terminations.

Terminate OUT1 and OUT1 with identical termination

on each for low output distortion. When a single-ended

signal is taken from the differential output, terminate

both OUT1 and OUT1.

Ensure that output currents do not exceed the current

limits as specified in the

Absolute Maximum Ratings

Under all operating conditions, the device’s total ther-

mal limits should be observed.

LVDS Output Termination

The MAX9376 LVDS outputs are current-steering

devices; no output voltage is generated without a termi-

nation resistor. The termination resistors should match

the differential impedance of the transmission line.

Output voltage levels are dependent upon the value of

the termination resistor. The MAX9376 is optimized for

point-to-point interface with 100Ω termination resistors

at the receiver inputs. Termination resistance values

may range between 90Ω and132Ω, depending on the

characteristic impedance of the transmission medium.

Supply Bypassing

Bypass V

to ground with high-frequency surface-

mount ceramic 0.1µF and 0.01µF capacitors. Place the

capacitors as close to the device as possible with the

0.01µF capacitor closest to the device pins.

Traces

Circuit board trace layout is very important to maintain

the signal integrity of high-speed differential signals.

Maintaining integrity is accomplished in part by reduc-

ing signal reflections and skew, and increasing com-

mon-mode noise immunity.

Signal reflections are caused by discontinuities in the

50Ω characteristic impedance of the traces. Avoid dis-

continuities by maintaining the distance between differ-

ential traces, not using sharp corners or using vias.

Maintaining distance between the traces also increases

common-mode noise immunity. Reducing signal skew

is accomplished by matching the electrical length of

the differential traces.

(MAX)

GND

(MIN)

80%

OUT2 - OUT2

20%

80%

DRV

OUT2

/ 2

VOD

VOD(+)

VOD(-)

VOS

GND

Figure 1. Input Definition

PHL

PLH

80%

20%

80%

DIFFERENTIAL OUTPUT

WAVEFORM

OR (V

- V

)

OR (V

- V

)

OR +(V

- V

)

-V

OR -(V

- V

)

0V DIFFERENTIAL

OUT

OUT - OUT

Figure 2. LVDS Output Load and Transition Times

Figure 3. Differential Input-to-Output Propagation Delay Timing

Diagram

P1-P3 P4-P6 P7-P8

MAX9376EUB+

Mfr. #:

Buy MAX9376EUB+

Manufacturer:

Maxim Integrated

Description:

Translation - Voltage Levels Single LVDS/Anything To-LVPECL/LVDS

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MAX9376EUB+

MAX9376EUB+

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