TDA19989_1 © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 01 — 15 February 2010 6 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
TX1+ B8 O positive data channel 1 for TMDS output
TX2− A7 O negative data channel 2 for TMDS output
TX2+ A6 O positive data channel 2 for TMDS output
TXC− G8 O negative clock channel for TMDS output
TXC+ F8 O positive clock channel for TMDS output
CEC H7 I/O CEC connection (open-drain) to HDMI connector
OSC_IN/AP3 H6 I input connected to the external oscillator circuit or external
clock source/audio port 3 input
AP2 G6 I audio port 2 input
VPA[0] C1 I video port A input bit 0 (LSB)
VPA[1] B1 I video port A input bit 1
VPA[2] B2 I video port A input bit 2
VPA[3] A2 I video port A input bit 3
VPA[4] B3 I video port A input bit 4
VPA[5] A3 I video port A input bit 5
VPA[6] B4 I video port A input bit 6
VPA[7] A4 I video port A input bit 7 (MSB)
VPB[0] E3 I video port B input bit 0 (LSB)
VPB[1] E2 I video port B input bit 1
VPB[2] E1 I video port B input bit 2
VPB[3] D1 I video port B input bit 3
VPB[4] D2 I video port B input bit 4
VPB[5] D3 I video port B input bit 5
VPB[6] C2 I video port B input bit 6
VPB[7] C3 I video port B input bit 7 (MSB)
VPC[0] H3 I video port C input bit 0 (LSB)
VPC[1] H2 I video port C input bit 1
VPC[2] G3 I video port C input bit 2
VPC[3] G2 I video port C input bit 3
VPC[4] G1 I video port C input bit 4
VPC[5] F1 I video port C input bit 5
VPC[6] F2 I video port C input bit 6
VPC[7] F3 I video port C input bit 7 (MSB)
V
DDA(TMDS)(1V8)
A8, C7 P TMDS analog supply voltage (1.8 V)
V
DDD(IO)(1V8)
E4 P I/O digital supply voltage (1.8 V)
V
DDA(PLL)(1V8)
C6 P PLL analog supply voltage (1.8 V), this PLL provides the clock
for the serializer
V
DDA(1V8)
G7, H8 P analog supply voltage (1.8 V), is used for parallel-to-serial
shift register and miscellaneous blocks
V
DDDC
E5 P core digital supply voltage (1.8 V)
Table 2. Pin description
…continued
Symbol Pin Type
[1]
Description
