TDA19989_1 © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 01 — 15 February 2010 37 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
13. Dynamic characteristics
[1] δ
clk
= t
clk(H)
/ (t
clk(H)
+ t
clk(L)
).
[2] See Section 7.1
and refer to the I
2
C-bus specification version 2.1 (document order number 9398 393 40011).
[3] For details about CEC electrical specification, see HDMI 1.3a specification.
Table 31. Timing characteristics
T
amb
=
−
20
°
Cto+85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock input: pin VCLK
f
clk(max)
maximum clock frequency - - - 148.5 MHz
t
su(D)
data input set-up time see Figure 18 and 19 1.5 - - ns
t
h(D)
data input hold time see Figure 18 and 19 1- - ns
δ
clk
clock duty cycle positive edge
[1]
30 50 70 %
f
clk
clock frequency CEC - 12 - MHz
DDC-bus: pins DSDA, DSCL (5 V tolerant) master bus
[2]
f
SCL
SCL frequency Standard mode - - 100 kHz
C
i
capacitance for each I/O pin - 7 - pF
I
2
C-bus: pins CSCL, CSDA (5 V tolerant) slave bus
[2]
f
SCL
SCL frequency Standard mode - - 100 kHz
Fast mode - - 400 kHz
t
stretch
stretch time CEC - 80 - μs
CEC input/output
[3]
t
r
rise time 10 % to 90 % - - 50 μs
t
f
fall time 10 % to 90 % - - 2 μs
TMDS output pins: TXC− and TXC+
f
clk(max)
maximum clock frequency on the TMDS link - - 148.5 MHz
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2− and TX2+
f
clk(max)
maximum clock frequency - - 1.485 GHz
