4
LTC1415
(Note 5)
TI I G CHARACTERISTICS
W
U
The denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above V
DD
,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above V
DD
without latchup.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below ground without latchup. These pins are not clamped
to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 1.25MHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A
IN
input with –A
IN
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 425ns after the start of the conversion or after BUSY rises.
Note 12: CS = RD = CONVST = 0V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency 1.25 MHz
Conversion and Acquisition Time
800 ns
t
CONV
Conversion Time 700 ns
t
ACQ
Acquisition Time 150 ns
t
1
CS to RD Setup Time (Notes 9, 10) 0ns
t
2
CS to CONVSTSetup Time (Notes 9, 10) 10 ns
t
3
NAP/SLPto SHDNSetup Time (Notes 9, 10) 200 ns
t
4
SHDN to CONVST Wake-Up Time Nap Mode (Note 10) 200 ns
Sleep Mode, C
REFCOMP
= 10µF (Note 10) 10 ms
t
5
CONVST Low Time (Notes 10, 11) 50 ns
t
6
CONVST to BUSY Delay C
L
= 25pF 10 ns
60 ns
t
7
Data Ready Before BUSY 20 35 ns
15 ns
t
8
Delay Between Conversions (Note 10) 50 ns
t
9
Wait Time RD After BUSY (Note 10) –5 ns
t
10
Data Access Time After RD C
L
= 25pF 20 35 ns
45 ns
C
L
= 100pF 25 45 ns
60 ns
t
11
Bus Relinquish Time 10 30 ns
0°C = T
A
= 70°C 35 ns
–40°C = T
A
= 85°C 40 ns
t
12
RD Low Time t
10
ns
t
13
CONVST High Time 50 ns
t
14
Aperture Delay of Sample-and-Hold 1.5 ns
5
LTC1415
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
INPUT FREQUENCY (Hz)
SIGNAL/(NOISE + DISTORTION) (dB)
80
70
60
50
40
30
20
10
0
1k 100k 1M 2M
LTC1415 • TPC01
10k
V
IN
= 0dB
V
IN
= –20dB
V
IN
= –60dB
S/(N + D) vs Input Frequency
and Amplitude
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
LTC1415 • TPC03
THD
2ND
3RD
1k 100k 1M 2M10k
Distortion vs Input Frequency
INPUT FREQUENCY (Hz)
SIGNAL-TO -NOISE RATIO (dB)
80
70
60
50
40
30
20
10
0
1k
LTC1415 • TPC02
100k 1M 2M10k
Signal-to-Noise Ratio vs
Input Frequency
Spurious-Free Dynamic Range vs
Input Frequency Intermodulation Distortion Plot
INPUT FREQUENCY (Hz)
10k
SPURIOUS-FREE DYNAMIC RANGE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100k 1M 2M
LTC1415 • TPC04
FREQUENCY (Hz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
100
120
200k 300k 600k
LTC1415 • TPC05
100k 400k 500k
fb – fa
2fb – fa
2fa – fb
2fa
2fb
3fb
fa + 2fb
3fa
2fa
+ fb
fa + fb
f
SAMPLE
= 1.25MHz
f
IN1
= 86.97509766kHz
f
IN2
= 113.2202148kHz
Integral Nonlinearity vs
Output Code
OUTPUT CODE
0
INL ERROR (LSBs)
1.00
0.50
0.00
0.50
1.00
512 1024 1536
LTC1415 • TPC07
2048 2560 3072 3584 4096
Differential Nonlinearity vs
Output Code
OUTPUT CODE
0
DNL ERROR (LSBs)
1.00
0.50
0.00
0.50
1.00
512 1024 1536
LTC1415 • TPC06
2048 2560 3072 3584 4096
6
LTC1415
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
Input Common Mode Rejection
vs Input Frequency
Power Supply Feedthrough vs
Ripple Frequency
RIPPLE FREQUENCY (Hz)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
1k 100k 1M 2M
LTC1415 • TPC08
10k
V
DD
OV
DD
DGND
INPUT FREQUENCY (Hz)
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
1k 100k 1M 2M
LTC1415 • TPC09
10k
PI FU CTIO S
UU U
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Its
rising edge may be used to latch the output data.
0V
DD
(Pin 26): Digital output buffer supply. Short to Pin
28 for 5V output. Tie to 3V for driving 3V logic.
DV
DD
(Pin 27): 5V Positive Supply. Short to Pin 28.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
+A
IN
(Pin 1): Positive Analog Input, 0V to 4.096V.
–A
IN
(Pin 2): Negative Analog Input, 0V to 4.096V.
V
REF
(Pin 3): 2.50V Reference Output.
REFCOMP (Pin 4): Bypass to AGND with 10µF tantalum
in parallel with 0.1µF or 10µF ceramic.
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Output Buffer Ground.
NAP/SLP (Pin 20): Power Shutdown Mode. High for
quick wake-up Nap mode.
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin. Tie high if unused.

LTC1415CG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 1.25Msps, 55mW Smpl A/D Conv
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union