7
LTC1643AL
LTC1643AL-1/LTC1643AH
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3V
SENSE
(Pin 10): The 3.3V Current Limit Set Pin. With a
sense resistor placed in the supply path between 3V
IN
and
3V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant voltage across the sense resistor and a con-
stant current through the switch. A foldback feature makes
the current limit decrease as the voltage at the 3V
OUT
pin
approaches GND. To disable the current limit, 3V
SENSE
and 3V
IN
can be shorted together.
GATE (Pin 11): High Side Gate Drive for the External
N-Channel Pass Transistors. Requires an external series
RC network for the current limit loop compensation and
setting the minimum ramp-up rate. During power-up, the
slope of the voltage rise at the GATE is set by the 62µA
current source connected to 12V
IN
and the external ca-
pacitor connected to GND or by the 3.3V or 5V current limit
and the bulk capacitance on the 3V
OUT
or 5V
OUT
suppy
lines. During power-down, the slope of the falling voltage
is set by the 200µA current source connected to GND and
the external GATE capacitor.
The voltage at the GATE pin will be modulated to maintain
a constant current when either the 3V or 5V supplies go
into current limit. When a current limit fault occurs after
the inhibit period set by the TIMER pin capacitance, the
undervoltage lockout circuit on 3.3V, 5V or 12V trips or
the FAULT pin is pulled low, the GATE pin is immediately
pulled to GND.
5V
SENSE
(Pin 12): 5V Current Limit Set Pin. With a sense
resistor placed in the supply path between 5V
IN
and
5V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant voltage across the sense resistor and a con-
stant current through the switch. A foldback feature makes
the current limit decrease as the voltage at the 5V
OUT
pin
approaches GND. To disable the current limit, 5V
SENSE
and 5V
IN
can be shorted together.
5V
IN
(Pin 13): Analog Input. Used to monitor the 5V input
supply voltage. An undervoltage lockout circuit prevents
the switches from turning on when the voltage at the 5V
IN
pin is less than 2.5V typically.
5V
OUT
(Pin 14): Analog Input. Used to monitor the 5V
output supply voltage. The PWRGD signal cannot go low
until the 5V
OUT
pin exceeds 4.65V typically.
the ON pin pulled low, the GATE pin is pulled high by a
62µA current source and the internal 12V and – 12V
switches are turned on. When the ON pin is pulled low or
the ON pin pulled high, the GATE pin will be pulled to
ground by a 200µA current source and the 12V and – 12V
switches turned off.
The ON/ON pin is also used to reset the electronic circuit
breaker. If the ON/ON pin is cycled following the trip of the
circuit breaker, the circuit breaker is reset and a normal
power-up sequence will occur.
FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low
when a current limit fault is detected. Current limit faults
are ignored while the voltage at the TIMER pin is less than
12V
IN
– 0.9V. Once the TIMER cycle is complete, FAULT
will pull low typically 14.6µs after any of the supplies go
into current limit. At the same time, the GATE and TIMER
pins are pulled to GND and the 12V and –12V switches are
turned off. The chip will remain latched in the off state until
the ON/ON pin is toggled or the power is cycled.
Forcing the FAULT pin low with an external pull-down will
immediately turn off the internal switches and force the
GATE and TIMER pins to GND independent of the state of
the ON/ON pin. However, the chip is not latched into the off
state, so when the FAULT pin is released, the state of the
chip will be determined by the ON pin.
PWRGD (Pin 7): Open-Drain Digital Power-Good Output.
PWRGD remains low while V
12VOUT
11.4V, V
3VOUT
3V,
V
5VOUT
4.75V and V
EEOUT
10.8V. The LTC1643AL-1
has the power good comparators connected to the 12V
OUT
and V
EEOUT
pins disabled, with only the 3V
OUT
and 5V
OUT
outputs being monitored to generate PWRGD. When one
of the supplies falls below its power-good threshold
voltage, PWRGD will go high after a 15µs deglitching time.
The switches will
not
be turned off when PWRGD goes
high.
GND (Pin 8): Chip Ground.
3V
IN
(Pin 9): 3.3V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 3V
IN
pin is less than 2.5V typically.
If no 3.3V input supply is available, tie 3V
IN
to the 5V
IN
pin.
PIN FUNCTIONS
UUU
8
LTC1643AL
LTC1643AL-1/LTC1643AH
1643afb
BLOCK DIAGRAM
W
+
+
+
+
LOGIC
9.5V
UVL
5V
OUT
+
3V
OUT
12V
IN
62µA
200µA
Q5
ON/ON
FAULT
22µA
3V
SENSEGATE
5V
IN
5V
SENSE
12V
IN
12V
OUT
V
EEIN
V
EEOUT
TIMER
GND
12V
IN
3V
IN
5V
OUT
3V
OUT
2.5V
UVL
2.5V
UVL
REF
REF
REF
LTC1643AH/LTC1643AL
ONLY
LTC1643AH/LTC1643AL
ONLY
Q2
Q8
REF
1643A BD
C
P3
+
+
+
C
P4
C
P5
C
P7
Q3
Q4
5
13
1 16 4 2 15 8
12 11 10 9 3 14
6
7
PWRGD
Q7
Q1
Q9
Q10
Q6
APPLICATIONS INFORMATION
WUU
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Hot Circuit Insertion
When a circuit board is inserted into a live PCI slot, the
supply bypass capacitors on the board can draw huge
transient currents from the PCI power bus as they charge
up. The transient currents can cause permanent damage
to the connector pins and cause glitches on the power bus,
causing other boards in the system to reset.
The LTC1643A is designed to turn a board’s supply
voltages on and off in a controlled manner, allowing the
board to be safely inserted or removed from a live PCI slot
without glitching the system power supplies. The chip
also protects the PCI supplies from shorts and monitors
the supply voltages.
The LTC1643AH is designed for motherboard applica-
tions, while the LTC1643AL/LTC1643AL-1 are designed
for CompactPCI applications where the chip resides on
the plug-in board.
V
EEOUT
(Pin 15):12V Supply Output. A 1.2 switch is
connected between V
EEIN
and V
EEOUT
. V
EEOUT
must
exceed –10.8V before the PWRGD signal can go high on
the LTC1643AH and LTC1643AL.
PIN FUNCTIONS
UUU
12V
OUT
(Pin 16): 12V Supply Output. A 0.5 switch is
connected between 12V
IN
and 12V
OUT
. 12V
OUT
must
exceed 11.4V before the PWRGD signal can go high on the
LTC1643AH and LTC1643AL.
9
LTC1643AL
LTC1643AL-1/LTC1643AH
1643afb
LTC1643A FEATURE SUMMARY
1. Allows safe board insertion and removal from either a
motherboard (LTC1643AH) or CompactPCI board
(LTC1643AL/LTC1643AL-1).
2. Controls all four PCI supplies: –12V, 12V, 3.3V and 5V.
3. Programmable foldback current limit: a programmable
analog current limit with a value that depends on the
output voltage. If the output is shorted to ground, the
current limit drops to keep power dissipation and
supply glitches to a minimum.
4. Programmable circuit breaker: if a supply remains in
current limit too long, the circuit breaker will trip, the
supplies will be turned off and the FAULT pin pulled low.
5. Current limit power-up: the supplies are allowed to
power up in current limit. Allows the chip to power up
boards with widely varying capacitive loads without
tripping the circuit breaker. The maximum allowable
power-up time is programmable using the TIMER pin.
6. –12V and 12V power switches on chip.
7. Power good output: monitors the voltage status of the
four supply voltages, except the LTC1643AL-1 which
only monitors 3V
OUT
and 5V
OUT
.
8. Space saving 16-pin SSOP package.
PCI Power Requirements
PCI systems usually require four power rails: 5V, 3.3V,
12V and –12V. Systems implementing the 3.3V signaling
environment are usually required to provide all four rails in
every system. Systems implementing the 5V signaling
environment may either ship the 3.3V supply with the
system or provide a means to add it afterward. The
tolerance of the supplies as measured at the components
on the plug-in card is summarized in Table 1.
APPLICATIONS INFORMATION
WUU
U
Some ±12V supplies in CompactPCI applications are not
well regulated and can violate the tolerance specification.
For these applications, the LTC1643AL-1 should be used
because the PWRGD signal does not depend on ±12V
outputs.
Power-Up Sequence
The power supplies are controlled by placing external
N-channel pass transistors in the 3.3V and 5V power
paths, and internal pass transistors for the 12V and –12V
power paths (Figure 1).
Resistors R1 and R2 provide current fault detection and
R7 and C1 provide current control loop compensation.
Resistors R5 and R6 prevent high frequency oscillations
in Q1 and Q2.
When the ON pin (Pin 5) is pulled high, the pass transistors
are allowed to turn on and a 22µA current source is
connected to the TIMER pin (Pin 4) (Figure 2).
The current in each pass transistor increases until it
reaches the current limit for each supply. Each supply is
then allowed to power up at the rate dv/dt = 62µA/C1 or as
determined by the current limit and the load capacitance
whichever is slower. Current limit faults are ignored while
the TIMER pin (Pin 4) voltage is ramping up and is less
than 0.9V below 12V
IN
(Pin 1). Once all four supply
voltages are within tolerance, the PWRGD pin (Pin 7) will
pull low.
Power-Down Sequence
When the ON pin (Pin 5) is pulled low, a power-down
sequence begins (Figure 3).
Internal switches are connected to each of the output
supply voltage pins to discharge the bypass capacitors to
ground. The TIMER pin (Pin 4) is immediately pulled low.
The GATE pin (Pin 11) is pulled down by a 200µA current
source to prevent the load currents on the 3.3V and 5V
supplies from going to zero instantaneously and glitching
the power supply voltages. When any of the output
voltages dip below its threshold, the PWRGD pin (Pin 7)
pulls high.
Table 1. PCI Power Supply Requirements
CAPACITIVE
SUPPLY TOLERANCE LOAD
5V 5V ±5% <3000µF
3.3V 3.3V ±0.3V <3000µF
12V 12V ±5% <500µF
12V –12V ±10% <120µF

LTC1643ALIGN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers PCI-Bus Hot Swap Cntr
Lifecycle:
New from this manufacturer.
Delivery:
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