NB6N14S
http://onsemi.com
2
Figure 3. NB6N14S Pinout, 16−pin QFN (Top View)
Q3 Q3
V
CC
EN
GND
IN
V
T
V
REF_AC
IN
Q1
Q1
Q2
Q2
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB6N14S
Exposed Pad (EP)
Q0 Q0 V
CC
IN IN EN Q
01 10
10 11
x x 0 0 (Note 1)
1. On next transition of the input signal (IN).
Table 1. TRUTH TABLE
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 Q1 LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q1 LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3 Q2 LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q2 LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 Q3 LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6 Q3 LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7 V
CC
− Positive Supply Voltage.
8 EN LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 23. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9 IN LVPECL, CML, LVDS Inverted Differential Input
10 V
REF_AC
LVPECL Output The V
REF_AC
reference output can be used to rebias capacitor−coupled
differential or single−ended input signals. For the capacitor−coupled IN and/or
INb inputs, V
REF_AC
should be connected to the VT pin and bypassed to
ground with a 0.01 mF capacitor.
11 V
T
LVPECL Output
Internal 100 W Center−tapped Termination Pin for IN and IN
12 IN LVPECL, CML, LVDS Non−inverted Differential Input. (Note 2)
13 GND − Negative Supply Voltage.
14 V
CC
− Positive Supply Voltage.
15 Q0 LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16 Q0 LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN
inputs, then the device will be susceptible to self−oscillation.
