Table 14: DDR2 I
DD
Specifications and Conditions (Die Revision E) – 2GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter
Sym-
bol -1GA
-80E/
-800 -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC
=
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs
are switching
I
DD0
1
976 776 736 616 616 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data pattern is
same as I
DD4W
I
DD1
1
1096 936 856 816 776 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable; Da-
ta bus inputs are floating
I
DD2P
2
112 112 112 112 112 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK
(I
DD
); CKE is HIGH, S# is HIGH; Other control and address bus inputs
are stable; Data bus inputs are floating
I
DD2Q
2
960 800 640 640 560 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are
switching; Data bus inputs are switching
I
DD2N
2
960 800 640 640 560 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
800 640 480 180 480 mA
Slow PDN ex-
it MR[12] = 1
160 160 160 160 160
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS
=
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
I
DD3N
2
1120 960 880 720 640 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
I
DD4W
1
1736 1336 1136 1056 896 mA
Operating burst read current: All device banks open; Continuous
burst read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH be-
tween valid commands; Address bus inputs are switching; Data bus
inputs are switching
I
DD4R
1
1736 1336 1136 1056 896 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs
are switching
I
DD5
2
4240 3760 3440 3360 3280 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are floating; Data bus inputs are floating
I
DD6
2
112 112 112 112 112 mA
512MB, 1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 UDIMM
I
DD
Specifications
PDF: 09005aef80f09084
htf16c64_128_256x64ay.pdf - Rev. G 3/10 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
