MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
18
Maxim Integrated
Initial Power-Up
The power-up sequence consists of an internal power-on
reset (POR), assertion of the external reset input RST,
and auto-address configuration (see the
Local 3-Wire
Interface
section). The internal POR resets all control
registers to the default values shown in Table 12.
After RST goes high an internal timer delays execution of
the auto-address configuration for 2
21
(2,097,152) OSC
cycles (nominally 250ms at OSC = 4.194MHz) (see the
3-Wire Interface Clock (ADDCLK)
section). During this
delay time, the global driver devices register (0x0E),
global driver rows register (0x0F), and global panel con-
figuration register (0x0D) should be written as these
values are used in the auto-address configuration
sequence (see the
Device Configuration
section). After
the internal delay time, the auto-addressing configuration
commences and takes a fixed interval of 256 ADDCLK
cycles to complete where the ADDCLK frequency is
OSC/4 (see the
3-Wire Interface Clock (ADDCLK)
sec-
tion). After completing the auto-self-addressing of all
possible 256 interconnected devices, all of the
MAX6960s enter shutdown mode.
All registers are capable of write device register opera-
tions during the internal delay interval using the 4-wire
serial interface. Read device register operations are not
allowed during auto-address configuration.
REGISTER DATA
REGISTER
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Global panel configuration 0x0D PI C F R DP1 DP0 IP S
Table 15. Global Panel Configuration Register Format
Table 16. Global Panel Configuration—Shutdown Control (S Data Bit D0) Format
REGISTER DATA
REGISTER
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Logic 1 in display memory lights the appropriate
LED (normal logic)
0x0D PI C F R DP1 DP0 0 S
Logic 0 in display memory lights the appropriate
LED (invert logic)
0x0D PI C F R DP1 DP0 1 S
Table 17. Global Panel Configuration—Invert Pixels (IP Data Bit D1) Format
REGISTER DATA
REGISTER
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Current display plane is P0 0x0D PI C F R 0 0 IP S
Current display plane is P1 0x0D PI C F R 0 1 IP S
Current display plane is P2 0x0D 0 C F R 1 0 IP S
Current display plane is P0 0x0D 1 C F R 1 0 IP S
Current display plane is P3 0x0D 0 C F R 1 1 IP S
Current display plane is P1 0x0D 1 C F R 1 1 IP S
Table 18. Global Panel Configuration—Current Plane (DP0, DP1 Data Bit D2, D3) Format
REGISTER DATA
REGISTER
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Shutdown 0x0D PI C F R DP1 DP0 IP 0
Normal operation 0x0D PI C F R DP1 DP0 IP 1
