Document Number: 38-07247 Rev. *O Page 14 of 17
Appendix: Silicon Errata for the Zero Delay Clock Buffers, CY2304
This section describes the errors, workaround solution and silicon design fixes for Cypress zero delay clock buffers belonging to the
families CY2304. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
CY2304 Errata Summary
CY2303 Qualification Status of fixed silicon
Product Status: In production
Qualification report last updated on 11/27/2012
http://www.cypress.com/?rID=72595
1. Start up lock time issue
■ Problem Definition
Output of CY2304 fails to locks within 1 ms upon power up (as per datasheet spec)
■ Parameters Affected
PLL lock time
■ Trigger Condition(s)
Start up
■ Scope of Impact
It can impact the performance of system and its throughput
■ Workaround
Apply reference input (RefClk) before power up (V
DD
). If RefClk is applied after power up, noise gets coupled on the output and
propagates back to the PLL causing it to take higher time to acquire lock. If reference input is present during power up, noise will
not propagate to the PLL and device will start up normally without problems.
■ Fix Status
This issue is due to design marginality. Two minor design modifications have been made to address this problem.
a. Addition of VCO bias detector block as shown in the following figure keeps comparator power down till VCO bias is present and
thereby eliminating the propagation of noise to feedback.
b. Bias generator enhancement for successful initialization.
Table 1. Part Numbers Affected
Part Number Device Variants
CY2304SXC-1 All Variants
CY2304SXC-1T All Variants
CY2304SXC-2 All Variants
CY2304SXC-2T All Variants
CY2304SXI-1 All Variants
CY2304SXI-1T All Variants
CY2304SXI-2 All Variants
CY2304SXI-2T All Variants
Items Part Number Fix Status
Start up lock time issue [CY2304] All Silicon fixed. New silicon available from WW 10 of 2013
