Document Number: 38-07247 Rev. *O Page 6 of 17
Switching Characteristics
For CY2304SXC Commercial Temperature Devices
Parameter
[5]
Name Test Conditions Min Typ Max Unit
t
1
Output frequency 30 pF load, all devices 10 – 100 MHz
t
1
Output frequency 15 pF load, -1, -2 devices 10 – 133.3 MHz
t
DC
Duty cycle
[6]
= t
2
t
1
(-1, -2)
Measured at 1.4 V,
F
OUT
= 66.66 MHz, 30-pF load
40.0 50.0 60.0 %
t
DC
Duty cycle
[6]
= t
2
t
1
(-2)
Measured at 1.4 V,
F
OUT
= 83.0 MHz, 15-pF load
40.0 50.0 60.0 %
t
DC
Duty cycle
[6]
= t
2
t
1
(-1, -2)
Measured at 1.4 V,
F
OUT
< 50 MHz, 15-pF load
45.0 50.0 55.0 %
t
3
Rise time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
30-pF load
– – 2.20 ns
t
3
Rise time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
15-pF load
– – 1.50 ns
t
4
Fall time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
30-pF load
– – 2.20 ns
t
4
Fall time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
15 pF load
– – 1.50 ns
t
5
Output-to-output skew on same
Bank (-1, -2)
[6]
All outputs equally loaded – – 200 ps
Output bank A to output bank B
skew (-1)
All outputs equally loaded – – 200 ps
Output bank A to output bank B
skew (-2)
All outputs equally loaded – – 400 ps
t
6
Skew, REF rising edge to FBK
rising edge
[6]
Measured at V
DD
/2 – 0 250 ps
t
7
Device-to-device skew
[6]
Measured at V
DD
/2 on the FBK pins
of devices
– 0 500 ps
t
J
Cycle-to-cycle jitter
[6]
(-1)
Measured at 66.67 MHz, loaded
outputs, 15-pF load
– 90 175 ps
Measured at 66.67 MHz, loaded
outputs, 30-pF load
– – 200 ps
Measured at 133.3 MHz, loaded
outputs, 15-pF load
– – 100 ps
t
J
Cycle-to-cycle jitter
[6]
(-2)
Measured at 66.67 MHz, loaded
outputs 30-pF load
– – 400 ps
Measured at 66.67 MHz, loaded
outputs 15-pF load
– – 375 ps
t
LOCK
PLL lock time
[6]
Stable power supply, valid clocks
presented on REF and FBK pins
– – 1.0 ms
Notes
5. All parameters are specified with loaded output.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.