1/11February 2003
■ 3.6V TOLERANT INPUTS AND OUTPUTS
■ HIGH SPEED :
t
PD
= 4.2 ns (MAX.) at V
CC
=3.0to3.6V
t
PD
= 5.3 ns (MAX.) at V
CC
=2.3to2.7V
t
PD
= 6.5 ns (MAX.) at V
CC
=1.65V
■ POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
= 24mA (MIN) at V
CC
=3.0V
|I
OH
|=I
OL
= 18mA (MIN) at V
CC
=2.3V
|I
OH
|=I
OL
=4mA(MIN)atV
CC
= 1.65V
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
■ BUS HOLD PROVIDED ON DATA INPUTS
■ LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
■ ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH16374 is a low voltage CMOS 16
BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C
2
MOS
technology. It is ideal for low power and very high
speed 1.65 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE
).
Onthepositivetransitionofthe(nCK),thenQ
outputs will be set to the logic state that were
setup at the nD inputs.
While the (nOE
) input is low, the outputs (nQ) will
be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state. Any output control does not
affect the internal operation of flip flops; that is, the
old data can be retained or the new data can be
entered even while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ALVCH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74ALVCH16374TTR
TSSOP
PIN CONNECTION
Obsolete Product(s) - Obsolete Product(s)
