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5.1 Configuration Register A (address 00h)
5.1.1 Master Clock Select
The STA320 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, Therefore the internal clock
will be:
32.768Mhz for 32kHz
45.1584Mhz for 44.1khz, 88.2kHz and 176.4kHz
49.152Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The
relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (Input
Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit deter-
mine the oversampling ratio used internally.
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0x1C B2cf3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0
0x1D A1cf1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16
0x1E A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8
0x1F A1cf3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0
0x20 A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16
0x21 A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8
0x22 A2cf3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0
0x23 B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16
0x24 B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8
0x25 B0cf3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0
0x26 Cfud RA R1 WA W1
0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
0x29 DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
0x2A DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0
0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8
0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0
0x2D Status PLLUL OCWARN TFAULT FAULT TWARN
0x2E BC0 RESRESRESRESRESRESRESRES
0x2F BS0 RESRESRESRESRESRESBS9 BS8
0x30 BS1 RESRESRESRESRESRESRESRES
0x31 B1 RESRESRESRESRESRESRESRES
0x32 B2 RESRESRESRESRESRESRESRES
0x33 T RESRESRESRESRESRESRESRES
D7 D6 D5 D4 D3 D2 D1 D0
FDRB TWAB TFRB IR1 IR0 MCS2 MCS1 MCS0
01100011
BIT R/W RST NAME DESCRIPTION
0 R/W 1 MCS0 Master Clock Select : Selects the ratio between the input
I
2
S sample frequency and the input clock.
1R/W 1 MCS1
2R/W 0 MCS2
Table 8. Register Summary (continued)
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Table 9.
5.1.2 Interpolation Ratio Select
The STA320 has variable interpolation (oversampling) settings such that internal processing and DDX output
rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through). or
provides a 2 times downsample.
The IR bits determine the oversampling ratio of this interpolation.
IR bit settings as a function of Input Sample Rate
Table 10.
Example: IR = 00, MCS = 011 (Default value):
XTI = 256 x fs = 8.192MHz (fs=32KHz) or 11.2896MHz (fs=44.1KHz) or 12.288MHz (fs=48KHz)
5.1.3 Thermal Warning Recovery Bypass
If the Thermal Warning Adjustment is enabled (TWAB=0), then the Thermal Warning Recovery will deter-
mine if the -3dB adjustment is removed when Thermal Warning is negative. If TWRB=0 and TWAB=0,
then when a thermal warning disappears the -3dB adjustment will be removed and the gain will be added
back to the system.
If TWRB=1 and TWAB=0, then when a thermal warning disappears the -3dB adjustment will remain until
TWRB is changed to zero or the device is reset.
Input Sample Rate
fs
(kHz)
IR MCS(2..0)
000 001 010 011 100 101
32, 44.1, 48 00 768fs 512fs 384fs 256fs 128fs 576fs
88.2, 96 01 384fs 256fs 192fs 128fs 64fs x
176.4, 192 1X 384fs 256fs 192fs 128fs 64fs x
BIT R/W RST NAME DESCRIPTION
4..3 R/W 00 IR(1..0) Interpolation Ratio Select: Selects internal interpolation ratio
based on input I
2
S sample frequency
Input Sample Rate
Fs
(kHz)
IR(1,0)
1
st
Stage Interpolation Ratio
32 00 2 times oversampling
44.1 00 2 times oversampling
48 00 2 times oversampling
88.2 01 Pass-Through
96 01 Pass-Through
176.4 10 2 times oversampling
192 10 2 times oversampling
BIT R/W RST NAME DESCRIPTION
5 R/W 1 TWRB Thermal-Warning Recovery Bypass:
0 - Thermal warning Recovery enabled
1 - Thermal warning Recovery disabled
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5.1.4 Thermal Warning Adjustable Bypass
The on-chip STA320 Power Output block provides feedback to the digital controller using inputs to the
Power Control block. The TWARN input is used to indicate a thermal warning condition.
When TWARN is asserted (set to 0) for a period of time greater than 400ms, the power control block will
force a -3dB adjustment to the modulation limit in an attempt to eliminate the thermal warning condition.
Once the thermal warning volume adjustment is applied, it remains in this state until reset.
5.1.5 hermal Warning Adjustable Bypass
The on-chip STA320 Power Output block provides feedback to the digital controller using inputs to the
Power Control block. The FAULT input is used to indicate a fault condition (either over-current or thermal).
When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by as-
serting the tri-state output (setting it to 0 which directs the power output block to begin recovery), hold it at
0 for period of time in the range of .1ms to 1 second as defined by the Fault-Detect Recovery Constant
register (FDRC registers 29-2Ah), then toggle it back to 1. This sequence is repeated as log as the fault
indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit
to 1.
5.2 Configuration Register B(Address 01h)
5.2.1 Serial Data Interface Format
5.2.2 Serial Data Interface
The STA320 audio serial input was designed to interface with standard digital audio components and to
accept a number of serial data formats. STA320 always acts a slave when receiving audio input from stan-
dard digital audio components. Serial data for two channels is provided using 3 inputs: left/right clock LRC-
KI, serial clock BICKI, and serial data 1 & 2 SDI12.
The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (Configuration Reg-
ister B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB-
First. Available formats are shown in the tables and figure that follow.
Table 11. Serial Data First Bit
BIT R/W RST NAME DESCRIPTION
6 R/W 1 TWAB Thermal-Warning Recovery Bypass:
0 - Thermal warning Recovery enabled
1 - Thermal warning Recovery disabled
BIT R/W RST NAME DESCRIPTION
7 R/W 0 FDRB Fault -Detector Recovery Bypass:
0 - Fault Detector Recovery enabled
1 - Fault Detector Recovery disabled
D7 D6 D5 D4 D3 D2 D1 D0
C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0
10000000
BIT R/W RST NAME DESCRIPTION
0 R/W 0 SAI0 Serial Audio Input Interface Format: Determines the interface
format of the input serial digital audio interface.
1R/W 0 SAI1
2R/W 0 SAI2
3R/W 0 SAI3
SAIFB Format
0MSB-First
1LSB-First

STA32013TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC AUD PROCESSOR 2.1MULTI 28SOIC
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