ISL6294IRZ-T

7
FN9174.4
July 9, 2007
Applications Information
Input Capacitor Selection
The input capacitor is required to suppress the power supply
transient response during transitions. Mainly this capacitor is
selected to avoid oscillation during the start up when the
input supply is passing the POR threshold and the VIN - BAT
comparator offset voltage. When the battery voltage is above
the POR threshold, the VIN - VBAT offset voltage dominates
the hysteresis value. Typically, a 1µF X5R ceramic capacitor
should be sufficient to suppress the power supply noise.
Output Capacitor Selection
The criteria for selecting the output capacitor is to maintain
the stability of the charger as well as to bypass any transient
load current. The minimum capacitance is a 1µF X5R
ceramic capacitor. The actual capacitance connected to the
output is dependent on the actual application requirement.
Charge Current Limit
The actual charge current in the CC mode is limited by
several factors in addition to the set I
REF
. Figure 1 shows
three limits for the charge current in the CC mode. The
charge current is limited by the on resistance of the pass
element (power P-Channel MOSFET) if the input and the
output voltage are too close to each other. The solid curve
shows a typical case when the battery voltage is 4.0V and
the charge current is set to 700mA. The non-linearity on the
r
ON
-limited region is due to the increased resistance at
higher die temperature. If the battery voltage increases to
higher than 4.0V, the entire curve moves towards right side.
As the input voltage increases, the charge current may be
reduced due to the thermal foldback function. The limit
caused by the thermal limit is dependent on the thermal
impedance. As the thermal impedance increases, the
thermal-limited curve moves towards left, as shown in
Figure 1.
Layout Guidance
The ISL6294 uses a thermally-enhanced DFN package that
has an exposed thermal pad at the bottom side of the
package. The layout should connect as much as possible to
copper on the exposed pad. Typically the component layer is
more effective in dissipating heat. The thermal impedance
can be further reduced by using other layers of copper
connecting to the exposed pad through a thermal via array.
Each thermal via is recommended to have 0.3mm diameter
and 1mm distance from other thermal vias.
Input Power Sources
The input power source is typically a well-regulated wall
cube with 1-meter length wire or a USB port. The input
voltage ranges from 4.25V to 6.5V under full-load and
unloaded conditions. The ISL6294 can withstand up to 28V
on the input without damaging the IC. If the input voltage is
higher than typically 6.8V, the charger stops charging.
6.5 4.0
700
INPUT VOLTAGE (V)
CHARGE CURRENT (mA)
4.5 5.0 5.5 6.0
θ
JA
or T
A
INCREASES
V
BAT
INCREASES
R
IREF
INCREASES
r
ON
LIMITED
THERMAL
LIMITED
ISL6294
FIGURE 1. CHARGE CURRENT LIMITS IN THE CC MODE
8
FN9174.4
July 9, 2007
ISL6294
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α
-
Rev. 1 6/05
9
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FN9174.4
July 9, 2007
ISL6294
Dual Flat No-Lead Plastic Package (DFN)
//
NX (b)
SECTION "C-C"
5
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C0.15
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BAMC
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
FOR EVEN TERMINAL/SIDE
TERMINAL TIP
C
L
e
L
CC
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.20 0.25 0.32 5,8
D 2.00 BSC -
D2 1.50 1.65 1.75 7,8
E 3.00 BSC -
E2 1.65 1.80 1.90 7,8
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N 8 2
Nd 4 3
Rev. 0 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

ISL6294IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Battery Management ISL6294 BATRY CHRGR 8LD 2X3
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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