74ABT16541CSSCX

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74ABT16541
DC Electrical Characteristics (Continued)
Note 3: Guaranteed but not tested.
Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
Extended AC Electrical Characteristics
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: The 3-STATE delay times are dominated by the RC network (500
, 250 pF) on the output and have been excluded from the datasheet.
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
ILD
Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 T
A
25 C (Note 5)
Symbol Parameter
T
A
25 CT
A
40 C to 85 C
Units
V
CC
5V V
CC
4.5V5.5V
C
L
50 pF C
L
50 pF
Min Typ Max Min Max
t
PLH
Propagation 1.0 2.3 3.4 1.0 3.4
ns
t
PHL
Delay Data to Outputs 1.0 2.7 3.9 1.0 3.9
t
PZH
Output Enable 1.5 3.5 5.2 1.5 5.2
ns
t
PZL
Time 1.5 3.5 6.0 1.5 6.0
t
PHZ
Output Disable 1.0 4.2 5.1 1.0 5.1
ns
t
PLZ
Time 1.0 3.2 5.1 1.0 5.1
Symbol Parameter
40 C to 85 C
T
A
40 C to 85 CT
A
40 C to 85 C
Units
V
CC
4.5V5.5V V
CC
4.5V5.5V V
CC
4.5V5.5V
C
L
50 pF C
L
250 pF C
L
250 pF
16 Outputs Switching 1 Output Switching 16 Outputs Switching
(Note 7) (Note 8) (Note 9)
Min Typ Max Min Max Min Max
f
TOGGLE
Maximum Toggle Frequency 100 MHz
t
PLH
Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.0
ns
t
PHL
Data to Outputs 1.5 5.3 1.5 6.0 2.5 8.0
t
PZH
Output Enable 1.5 6.5 2.5 7.8 2.5 9.5
ns
t
PZL
Time 1.5 6.5 2.5 7.8 2.5 8.5
t
PHZ
Output Disable 1.0 6.7 (Note 10) (Note 10) ns
t
PLZ
Time 1.0 6.7
5 www.fairchildsemi.com
74ABT16541
Skew
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
). The specification is guaranteed but not tested.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Capacitance
Note 16: C
OUT
is measured at frequency f 1 MHz; per MIL STD-883, Method 3012.
Symbol Parameter
T
A
40 C to 85 CT
A
40 C to 85 C
Units
V
CC
4.5V5.5V V
CC
4.5V5.5V
C
L
50 pF C
L
250 pF
16 Outputs Switching 16 Outputs Switching
(Note 11) (Note 12)
Max Max
t
OSHL
Pin to Pin Skew
1.0 1.5 ns
(Note 13) HL Transitions
t
OSLH
Pin to Pin Skew
1.0 1.5 ns
(Note 13) LH Transitions
t
PS
Duty Cycle
1.5 1.5 ns
(Note 14) LHHL Skew
t
OST
Pin to Pin Skew
1.7 2.0 ns
(Note 13) LH/HL Transitions
t
PV
Device to Device Skew
2.0 2.5 ns
(Note 15) LH/HL Transitions
Symbol Parameter Typ Units
Conditions
T
A
25 C
C
IN
Input Capacitance 5.0 pF V
CC
5.0V
C
OUT
(Note 16) Output Capacitance 9.0 pF V
CC
5.0V
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74ABT16541
AC Loading
* Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Pulse Requirements
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 6. 3-STATE Output HIGH and LOW Enable and
Disable Times
FIGURE 7. Setup Time, Hold Time and Recovery Time
Waveforms
Amplitude Rep Rate t
W
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

74ABT16541CSSCX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Buffers & Line Drivers 16-Bit Buf/Line Drv
Lifecycle:
New from this manufacturer.
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