..........................Document #: 38-07372 Rev. *B Page 6 of 9
AC Parameters V
DD
= V
DDQ
= 2.5V ± 5%, T
A
= 0°C to +70°C
[10,11]
Parameter Description Condition Min. Typ. Max. Unit
fCLK Operating Clock Frequency AV
DD
, V
DD
= 2.5V ± 0.2V 60 170 MHz
tDC Input Clock Duty Cycle 40 60 %
tlock Maximum PLL lock Time 100 s
Tr / Tf Output Clocks Slew Rate 20% to 80% of V
OD
1 2.5V/ns
tpZL, tpZH Output Enable Time
[12]
(all outputs) 3 ns
tpLZ, tpHZ Output Disable Time
[12]
(all outputs) 3 ns
tCCJ Cycle to Cycle Jitter f > 66 MHz –100 100 ps
tjit(h-per) Half-period jitter
[14]
f > 66 MHz –100 100 ps
tPLH
Low-to-High Propagation Delay,
CLKINT to CLKT[0:5]
1.5 3.5 6 ns
tPHL
High-to-Low Propagation Delay,
CLKINT to CLKT[0:5]
1.5 3.5 6 ns
tSKEW Any Output to Any Output Skew
[13]
100 ps
tPHASE Phase Error
[13]
–150 150 ps
tPHASEJ Phase Error Jitter f > 66MHz –50 50 ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple-
mentary input level.
6. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing.
7. For load conditions see Figure 7.
8. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See Figure 7.
9. All outputs switching loaded with 16 pF in 60 environment. See Figure 7.
10.Parameters are guaranteed by design and characterization. Not 100% tested in production.
11.PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of –0.5%.
12.Refers to transition of non-inverting output.
