9DB401CGLF Datasheet 9DB401CGLF, 9DB401CGLFT, 9DB401CFLFT | P10-P12

IDT

Four Output Differential Buffer for PCI Express 9DB401C REV H 01/27/11

9DB401C

Four Output Differential Buffer for PCI Express

SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)

Pin # Name Control Function T

e0 1 PWD

Bit 7

PD_Mode PD# drive mode RW driven Hi-Z 0

Bit 6

STOP_Mode SRC_Stop# drive mode RW driven Hi-Z 0

Bit 5

PD_SRC_INV

Power Down

and SRC Invert

RW Normal Invert 0

Bit 4

Reserved Reserved RW X

Bit 3

Reserved Reserved RW X

Bit 2

PLL_BW# Select PLL BW RW Hi

h BW Low BW 1

Bit 1

BYPASS# BYPASS#/PLL RW fan-out ZDB 1

Bit 0

SRC_DIV# SRC Divide by 2 Select RW x/2 1x 1

SMBus Table: Output Control Register

Pin # Name Control Function T

e0 1 PWD

Bit 7

Reserved Reserved RW X

Bit 6

DIF_6 Output Control RW Disable Enable 1

Bit 5

DIF_5 Output Control RW Disable Enable 1

Bit 4

Reserved Reserved RW X

Bit 3

Reserved Reserved RW X

Bit 2

DIF_2 Output Control RW Disable Enable 1

Bit 1

DIF_1 Output Control RW Disable Enable 1

Bit 0

Reserved Reserved RW X

SMBus Table: Output Control Register

Pin # Name Control Function T

e0 1 PWD

Bit 7

Reserved Reserved RW X

Bit 6

DIF_6 Output Control RW Free-run Stoppable 0

Bit 5

DIF_5 Output Control RW Free-run Stoppable 0

Bit 4

Reserved Reserved RW X

Bit 3

Reserved Reserved RW X

Bit 2

DIF_2 Output Control RW Free-run Stoppable 0

Bit 1

DIF_1 Output Control RW Free-run Stoppable 0

Bit 0

Reserved Reserved RW X

SMBus Table: Output Control Register

Pin # Name Control Function T

e0 1 PWD

Bit 7

RW X

Bit 6

RW X

Bit 5

RW X

Bit 4

RW X

Bit 3

RW X

Bit 2

RW X

Bit 1

RW X

Bit 0

RW X

Reserved Reserved

6,7

te 3

19,20

9,10

te 2

22,23

9,10

6,7

te 1

22,23

19,20

-Reserved

te 0

Reserved

IDT

Four Output Differential Buffer for PCI Express 9DB401C REV H 01/27/11

9DB401C

Four Output Differential Buffer for PCI Express

SMBus Table: Vendor & Revision ID Register

Pin # Name Control Function T

e0 1 PWD

Bit 7

RID3 R - - X

Bit 6

RID2 R - - X

Bit 5

RID1 R - - X

Bit 4

RID0 R - - X

Bit 3

VID3 R - - 0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

SMBus Table: DEVICE ID

Pin # Name Control Function T

e0 1 PWD

Bit 7

RW 0

Bit 6

RW 1

Bit 5

RW 0

Bit 4

RW 0

Bit 3

RW 0

Bit 2

RW 0

Bit 1

RW 0

Bit 0

RW 1

SMBus Table: Byte Count Register

Pin # Name

Control

Function

Type 0 1 PWD

Bit 7

BC7 RW - - 0

Bit 6

BC6 RW - - 0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3 RW - - 0

Bit 2

BC2 RW - - 1

Bit 1

BC1 RW - - 1

Bit 0

BC0 RW - - 1

Device ID 3 Reserved

Device ID 0 Reserved

Device ID 2 Reserved

Device ID 1 Reserved

Device ID 5 Reserved

Device ID 4 Reserved

Device ID 6 Reserved

Device ID 7 (MSB) Reserved

Byte 6

Writing to this register

configures how many bytes

will be read back.

te 5

VENDOR ID

te 4

REVISION ID

IDT

Four Output Differential Buffer for PCI Express 9DB401C REV H 01/27/11

9DB401C

Four Output Differential Buffer for PCI Express

The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting

off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the

device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#

drive mode and Output control bits) before the PLL is shut down.

PD#

When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending

on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode

bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x I

REF

and DIF# tri-stated. If the PD# drive mode bit is

set to ‘1’, both DIF and DIF# are tri-stated.

PD# Assertion

Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from

valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set

to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.

PD# De-assertion

PWRDWN#

DIF

DIF#

PWRDWN#

DIF

DIF#

Tstable

<1mS

Tdrive_PwrDwn#

<300uS, >200mV

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

9DB401CGLF

Mfr. #:

Buy 9DB401CGLF

Manufacturer:

IDT

Description:

Clock Buffer 4-output Differential Buffer For PCI Express

Lifecycle:

New from this manufacturer.

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9DB401CGLF

9DB401CGLF

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