Data Sheet ADF4106
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
02720-003
R
SET
CP
CPGND
AGND
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
V
P
DV
DD
TOP VIEW
(Not to Scale)
ADF4106
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
Figure 3. 16-Lead TSSOP Pin Configuration
02720-004
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11
CE
CPGND
AGND
2
AGND
RF
IN
B
5
RF
IN
A
7
AV
DD
6
AV
DD
8
REF
IN
9
DGND
10
DGND
19
R
SET
20
CP
18
V
P
17
DV
DD
16
DV
DD
ADF4106
TOP VIEW
(Not to Scale)
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. 20-Lead LFCSP_WQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
Pin No.
LFCSP Mnemonic Function
1 19 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
So, with R
SET
= 5.1 kΩ, I
CP MAX
= 5 mA.
2 20 CP
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn
drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
IN
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
6 5 RF
IN
A Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 6, 7 AV
DD
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
11 12 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
14 15 MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
15 16, 17 DV
DD
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
DD
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP Exposed Pad. The exposed pad must be connected to AGND.
Rev. F | Page 7 of 24
