Z86C83/C84/E83
CMOS Z8
®
MCU Zilog
8-36 P R E L I M I N A R Y DS97DZ80700
FUNCTIONAL DESCRIPTION (Continued)
Figure 27 shows the input circuit of the ADC. When con-
version starts the analog input voltage is connected to the
MSB and LSB flash converter inputs as shown in the Input
Impedance CKT diagram. Effectively, shunting 31 parallel
internal resistance of the analog switches and simulta-
neously charging 31 parallel 0.5 pF capacitors, which is
equivalent to seeing a 400 Ohms input impedance in par-
allel with a 16 pF capacitor. Other input stray capacitance
adds about 10 pF to the input load. For input source resis-
tances up to 2 Kohms can be used under normal operating
condition without any degradation of the input settling time.
For larger input source resistance, increasing conversion
cycle time or adding a capacitor to the input may be re-
quired to compensate the input settling time problem.
Typical Z8 A/D Conversion Sequence
3. Set the register pointer to Extended Bank (C), that is,
SRP #%0C instruction.
4. Next, set ADE flag by loading ADC1 Control Register
Bank (C) Register 9, bit 7. Also, load bits 0-4 of this
same register to select a AV
CC
or A
GND
offset value. A
precision voltage divider connected to the A/D
resistive ladder can offset conversion dynamic range
to specified limits within the AV
CC
and A
GND
limits. By
loading Bank (C) Register 9, bits 0-4, with the
appropriate value it is possible to select from these
groups:
a. No Offset. The Converter Dynamic range is from
0V to 5.0V for AV
CC
= 5.0V.
b. 35 Percent A
GND
Offset. The Converter Dynamic
range is 1.75V - 5.0V for AV
CC
= 5.0V.
c. 50 Percent A
GND
Offset. The Converter Dynamic
range is 2.5V - 5.0V for AV
CC
= 5.0V.
5. Select one of the eight A/D inputs for conversion by
loading Bank (C) Register 8 with the desired attributes:
Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D
conversion (or digital port I/O).
6. Set Bank (C) Register 8, bit 3 to enable A/D
conversion. (This flag can be set concurrently with
step 3.) This flag is automatically reset when the A/D
conversion is completed, so a bit test can be
performed to determine A/D readiness if necessary.
7. Read the A/D result in Bank (C) Register A. Please
note that the A/D result is not valid (indeterminate)
unless ADE flag (Register 9, bit 7) was previously set,
otherwise A/D converter output is tri-stated.
Figure 27. Input Impedance of ADC
CMOS Switch
on Resistance
2 - 5 k Ω
C Parasitic
R Source
C .5 pF
V Ref
C .5 pF
C .5 pF
31 CMOS Digital
Comparators