Z86C83/C84/E83
CMOS Z8
®
MCU Zilog
8-40 P R E L I M I N A R Y DS97DZ80700
In order to enter STOP (or HALT) Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (Opcode = FFH) immediately before the appropri-
ate sleep instruction, that is,
Stop-Mode Recovery (SMR) Register. This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 34 and Figure 35). All bits
are Write-Only, except bit 7, which is Read-Only. Bit 7 is a
flag bit that is hardware set on the condition of STOP re-
covery and reset by a power-on cycle. Bit 6 controls wheth-
er a low level or a high level is required from the recovery
source. Bit 5 controls the reset delay after recovery. Bits 2,
3, and 4, or the SMR Register, specify the source of the
Stop-Mode Recovery signal. Bits 0 and 1 determine the
time-out period of the WDT. The SMR Register is located
in Bank F of the Expanded Register Group at address
0BH. When the Stop-Mode Recovery sources are selected
in this register, then SMR2 Register bits D0,D1 must be set
to 0.
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The con-
trol selectively reduces device power consumption during
normal processor execution (SCLK control) and/or HALT
mode (where TCLK sources counter/timers and interrupt
logic). This bit is reset to D0 = 0 after a Stop-Mode Recov-
ery, WDT Time-out, and POR.
External Clock Divide-by-Two (D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock HALT Mode frequency divided
by two. The SCLK/TCLK is equal to the external clock fre-
quency when this bit is set (D1=1). Using this bit together
with D7 of PCON further helps lower EMI (that is, D7
(PCON) = 0, D1 (SMR) = 1). The default setting is zero.
Maximum external clock frequency is 8 MHz when SMR
Bit D1 = 1 where SCLK/TCLK = XTAL.
FF NOP ; clear the pipeline
6F STOP ; enter STOP Mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT Mode
Figure 34. Stop-Mode Recovery Register (Write-Only
Except Bit D7, Which Is Read-Only)
D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B
SCLK/TCLK Divide-by-16
0 OFF* *
1 ON
Stop-Mode Recovery Source
000 POR Only and/or External Reset*
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON
Stop Recovery Level
0 Low *
1 High
Stop Flag (Read-Only)
0 POR
1 Stop Recovery
Note: Not used in conjunction with SMR2
Source
* Default Setting After RESET
** Default setting after RESET and
Stop-Mode Recovery
*
*
External Clock Divide-by-2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL
Figure 35. Stop-Mode Recovery Register 2
([0F] DH: Write-Only)
Figure 36. SCLK Circuit
D7 D6 D5 D4 D3 D2 D1 D0
SMR2 (0F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
SMR, D0
÷ 2
÷16
OSC
SCLK
TCLK
SMR, D1
