Z86C83/C84/E83
Zilog CMOS Z8
®
MCU
DS97DZ80700 P R E L I M I N A R Y 8-47
1
Figure 58. Port 2 Mode Register (F6
H
: Write-Only)
Figure 59. Port 0 and 1 Mode Register
(F8
H
: Write-Only)
Figure 60. Interrupt Priority Register (F9
H
: Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
P27- P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
R246 P2M
*Default Setting After Reset
D7 D6 D5 D4 D3 D2 D1 D0
P00-P03 Mode †
00 Output
01 Input
1X A11-A8
R248 P01M
Reserved (Must be 1)
Reserved (Must be 0)
P04-P06 Mode
00 Output
01 Input
1X A15-A12
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0)
R249 IPR
Figure 61. Interrupt Request Register
(F
AH
: Read/Write)
Figure 62. Interrupt Mask Register (F
BH
: Read/Write)
Figure 63. Flag Register (F
CH
: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = Software Controlled
IRQ4 = T0
IRQ5 = T1
Inter Edge
00 P31 ↓
01 P31 ↓
10 P31 ↑
11 P31 ↑↓
R250 IRQ
Default Setting After Reset = 00H
P32 ↓
P32 ↑
P32 ↓
P32 ↑↓
D7 D6 D5 D4 D3 D2 D1 D0
1 RAM Protect Enabled
0 RAM Protect Disabled *
1 Enables IRQ5-IRQ0
(D0 = IRQ0)
1 Enables Interrupts
0 Disable interrupts
* (Default setting after RESET.)
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
R252 Flags
