MAX195BEWE+ Datasheet MAX195BCWE+, MAX195BCPE+, MAX195BEWE+T | P16-P18

MAX195

If ±15V supplies are unavailable, Figure 16’s circuit

works very well with the ±5V analog supplies used by

the MAX195. The MAX410 has a minimum ±3.5V com-

mon-mode input range, with a similar output voltage

swing, which allows use of a reference voltage up to

3.5V. The offset voltage (250µV) is about 2LSB. The

drift (1µV/°C), unity-gain bandwidth (28MHz), and low

voltage noise (2.4nV/√Hz) are appropriate for 16-bit

performance.

Operating Modes and SPI/QSPI Interfaces

The two basic interface modes are defined according

to whether serial data is received during the conversion

(clocked with CLK, SCLK unused) or in bursts between

conversions (clocked with SCLK). Each mode is pre-

sented interfaced to a QSPI processor, but is also com-

patible with SPI.

Mode 1 (Simultaneous

Conversion and Data Transfer)

In this mode, each data bit is read from the MAX195

during the conversion as it is determined. SCLK is

grounded and CLK is used as both the conversion

clock and the serial data clock. Figure 17 shows a

QSPI processor connected to the MAX195 for use in

this mode and Figure 18 is the associated timing dia-

gram.

In addition to the standard QSPI interface signals, gen-

eral I/O lines are used to monitor EOC and to drive

BP/UP/SHDN and RESET. The two general output pins

may not be necessary for a given application and, if I/O

lines are unavailable, the EOC connection can be omit-

ted as well.

The EOC signal is monitored during calibration to

determine when calibration is finished and before

beginning a conversion to ensure the MAX195 is not in

mid-conversion, but it is possible for a system to ignore

EOC completely. On power-up or after pulsing RESET

low, the µP must provide 14,000 CLK cycles to com-

plete the calibration sequence (Figure 2). One way to

do this is to toggle CLK and monitor EOC until it goes

low, but it is possible to simply count 14,000 CLK

cycles to complete the calibration. Similarly, it is

unnecessary to check the status of EOC before begin-

ning a conversion if you are sure the last conversion is

complete. This can be done by ensuring that every

conversion consists of at least 20 CLK cycles.

Data is clocked out of the MAX195 on CLK’s falling

edge and can be clocked into the µP on the rising

edge or the following falling edge. If you clock data in

on the rising edge (SPI/QSPI with CPOL = 0 and CPHA

= 0; standard MicroWire™: Hitachi H8), the maximum

CLK rate is given by:

where t

is the MAX195’s CLK-to-DOUT valid delay

and t

is the data setup time for your µP.

f = /

t + t

CLK(max)

CD SD













16-Bit, 85ksps ADC with 10µA Shutdown

16 ______________________________________________________________________________________

MAX195

QSPI

GPT

BP/UP/SHDN

CLK

SCLK

EOC

DOUT

RESET

CONV

*OC3

SCK

*IC1

MISO

*OC2

* THE USE OF THESE SIGNALS ADDS FLEXIBILITY AND FUNCTIONALITY

BUT IS NOT REQUIRED TO IMPLEMENT THE INTERFACE.

PCS0

Figure 17. MAX195 Connection to QSPI Processor Clocking

Data Out During Conversions

MAX410

+5V

-5V

0.1µF

0.01µF

22Ω

510Ω

0.1µF

AIN

Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing

MicroWire is a trademark of National Semiconductor Corp.

If clocking data in on the falling edge (CPOL = 0,

CPHA = 1), the maximum CLK rate is given by:

Do not exceed the maximum CLK frequency given in

the

Electrical Characteristics

table. To clock data in on

the falling edge, your processor hold time must not

exceed t

minimum (100ns).

While QSPI can provide the required 20 CLK cycles as

two continuous 10-bit transfers, SPI is limited to 8-bit

transfers. This means that with SPI, a conversion must

consist of three 8-bit transfers. Ensure that the pauses

between 8-bit operations at your selected clock rate

are short enough to maintain a 20ms or shorter conver-

sion time, or the leakage of the capacitive DAC may

cause errors.

Complete source code for the Motorola 68HC16 and

the MAX195 evaluation kit (EV kit) using this mode is

available with the MAX195 EV kit.

Mode 2 (Asynchronous Data Transfer)

This mode uses a conversion clock (CLK) and a serial

clock (SCLK). The serial data is clocked out between

conversions, which reduces the maximum throughput

for high CLK rates, but may be more convenient for

some applications. Figure 19 is a block diagram with a

QSPI processor (Motorola 68HC16) connected to the

MAX195. Figure 20 shows the associated timing dia-

gram. Figure 21 gives an assembly language listing for

this arrangement.

f =

t + t

CLK(max)

CD SD

MAX195

16-Bit, 85ksps ADC with 10µA Shutdown

______________________________________________________________________________________ 17

EOC

CLK

DATA LATCHED:

CS, CONV

DOUT

B15 FROM PREVIOUS

CONVERSION

B15 B15B2B14 B1 B0

MAX195

QSPI

GPT

BP/UP/SHDN

SCLK

EOC

DOUT

RESET

CONV

1.7MHz

CLKIC3

OC3

SCK

IC1

MISO

OC2

START

PCS0

1.3µs

74HC32

Figure 19. MAX195 Connection to QSPI Processor Clocking

Data Out with SCLK Between Conversions

Figure 18. Timing Diagram for Circuit of Figure 17 (Mode 1)

MAX195

An OR gate is used to synchronize the “start” signal to

the asynchronous CLK, as described in the

External

Clock

section. As with Mode 1, the QSPI processor must

run CLK during calibration and either count CLK cycles

or, as is done here, monitor EOC to determine when cal-

ibration is complete. Also, EOC is polled by the µP to

determine when a conversion result is available. When

EOC goes low, data is clocked out at the highest QSPI

data rate (4.19Mbps). After the data is transferred, a

new conversion can be initiated whenever desired.

The timing specification for SCLK-to-DOUT valid (t

)

imposes some constraints on the serial interface. At

SCLK rates up to 2.5Mbps, data is clocked out of the

MAX195 by a falling edge of SCLK and may be

clocked into the µP by the next rising edge (CPOL = 0,

CPHA = 0). For data rates greater than 2.5Mbps (or for

lower rates, if desired) it is necessary to clock data out

of the MAX195 on SCLK’s falling edge and to clock it

into the µP on SCLK’s next falling edge (CPOL = 0,

CPHA = 1). Also, your processor hold time must not

exceed t

minimum (20ns). As with CLK in mode 1,

maximum SCLK rates may not be possible with some

interface specifications that are subsets of SPI.

Supplies, Layout, Grounding

and Bypassing

For best system performance, use printed circuit

boards with separate analog and digital ground planes.

Wire-wrap boards are not recommended. The two

ground planes should be tied together at the low-

impedance power-supply source and at the MAX195

(Figure 22.) If the analog and digital supplies come

from the same source, isolate the digital supply from

the analog supply with a low-value resistor (10Ω).

Constraints on sequencing the four power supplies are

as follows.

• Apply VDDA before VDDD.

• Apply VSSA before VSSD.

• Apply AIN and REF after VDDA and VSSA are present.

• The power supplies should settle within the

MAX195’s power-on delay (minimum 500ns) or you

should recalibrate the converter (pulse RESET low)

before use.

16-Bit, 85ksps ADC with 10µA Shutdown

18 ______________________________________________________________________________________

CLK

START

588ns

239ns

CONVERSION TIME

4.19MHz

1.3µs 9.4µs 17µs* 5.1µs

4µs

EOC

SCLK

DOUT

B15 B3 B2B13B14 B1 B0

* INTERRUPT LATENCY OF THE PROCESSOR

Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

MAX195BEWE+

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Analog to Digital Converters - ADC 16-Bit 85ksps 5V Precision ADC

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