PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 5 of 24
NXP Semiconductors
PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
is activated during the initialization and is deactivated when the connection is made. The
precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 kΩ
nominal resistors. This precharges the pins to 1 V to minimize the worst case
disturbances that result from inserting a card into the backplane where the backplane and
the card are at opposite logic levels.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that
isolates the input capacitance from the output bus capacitance while communicating the
logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be
driven to a LOW by the part. The same is also true for the SCL pins. Noise between
0.7V
CC
and V
CC
is generally ignored because a falling edge is only recognized when it
falls below 0.7V
CC
with a slew rate of at least 1.25 V/µs. When a falling edge is seen on
one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small
voltage above the falling pin. The driver will pull the pin down at a slew rate determined by
the driver and the load initially, because it does not start until the first falling pin is below
0.7V
CC
. The first falling pin may have a fast or slow slew rate, if it is faster than the pull
down slew rate then the initial pull-down rate will continue. If the first falling pin has a slow
slew rate then the second pin will be pulled down at its initial slew rate only until it is just
above the first pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will rise until the internal
driver pulls it down to the offset voltage. When the last external driver stops driving a
LOW, that pin will rise up and settle out just above the other pin as both rise together with
a slew rate determined by the internal slew rate control and the RC time constant. As long
as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V for the
PCA9511A, the rise time accelerator’s circuits are turned on and the pull-down driver is
turned off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher
temperatures. Maximum offset (V
offset
) is 0.150 V with a 10 kΩ pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is that the I
2
C-bus specification of 3 mA will produce V
OL
< 0.4 V,
although if lightly loaded the V
OL
may be ~0.1 V. Assuming V
OL
= 0.1 V and V
offset
= 0.1 V,
the level after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of
the rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the V
OL
moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
