© 2002 Fairchild Semiconductor Corporation DS500406 www.fairchildsemi.com
April 2001
Revised June 2002
74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs
74LCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 5V Tolerant Inputs and Outputs
General Description
These 36-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transpar-
ent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA
), latch-enable (LEAB and LEBA), and
clock (CLKAB
and CLKBA) inputs.
The LCX32500 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with the capability of interfacing to a 5V
signal environment.
The LCX32500 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V V
CC
specifications provided
■ 6.0 ns t
PD
max (V
CC
= 3.3V), 20 µA I
CC
max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■
±24 mA output drive (V
CC
= 3.0V)
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model
> 2000V
Machine model
> 200V
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74LCX32500G
(Note 2)(Note 3)
BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
