SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 39 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
10. Dynamic characteristics
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] 10 % of the data bus output voltage level.
[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Table 37. Dynamic characteristics - Intel or 16 mode
T
amb
=
40
C to +85
C; V
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
WH
pulse width HIGH 6 - - ns
t
WL
pulse width LOW 6 - - ns
t
w(clk)
clock pulse width 12.5 - - ns
f
XTAL1
frequency on pin XTAL1
[1][2]
--80MHz
t
su(A)
address set-up time 0 - - ns
t
h(A)
address hold time 10 - - ns
t
d(CS-IOR)
delay time from CS to IOR 5- - ns
t
w(IOR)
IOR pulse width time 20 - - ns
t
h(IOR-CS)
hold time from IOR to chip select 0 - - ns
t
d(IOR)
IOR delay time 10 - - ns
t
d(IOR-Q)
delay time from IOR to data output 25 pF load - - 40 ns
t
dis(IOR-QZ)
disable time from IOR to high-impedance
data output
[3]
25 pF load - - 20 ns
t
d(CSL-IOWL)
delay time from CS LOW to IOW LOW 5 - - ns
t
w(IOW)
IOW pulse width time 10 - - ns
t
h(IOW-CS)
hold time from IOW to CS 0- - ns
t
d(IOW)
IOW delay time 10 - - ns
t
su(D-IOWH)
set-up time from data input to IOW HIGH 5 - - ns
t
h(IOWH-D)
data input hold time after IOW HIGH 5 - - ns
t
d(IOW-Q)
delay time from IOW to data output 25 pF load - - 50 ns
t
d(modem-INT)
delay time from modem to INT 25 pF load - - 50 ns
t
d(IOR-INTL)
delay time from IOR to INT LOW 25 pF load - - 50 ns
t
d(stop-INT)
delay time from stop to INT 25 pF load
[4]
--1T
RCLK
s
t
d(start-INT)
delay time from start to INT 25 pF load
[4]
--1T
RCLK
s
t
d(IOW-TX)
delay time from IOW to TX 25 pF load
[4]
8T
RCLK
-24T
RCLK
s
t
d(IOW-INTL)
delay time from IOW to INT LOW 25 pF load - - 50 ns
t
w(RESET)
pulse width on pin RESET 10 - - ns
N baud rate divisor 1 - (2
16
1)
1
t
wclk
---------------
