6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
AC Test Conditions
Timing of Power-Up Power-Down
Figure 1. AC Output Test Load
Figure 2. Output Test Load
*Including scope and jig.
(For t
LZ, tHZ, tWZ, tOW)
CE
2941 drw 06
t
PU
I
CC
I
SB
t
PD
50%
50%
sleveLesluPtupnI
semiTllaF/esiRtupnI
sleveLecnerefeRgnimiTtupnI
sleveLecnerefeRtuptuO
daoLtuptuO
V0.3otDNG
.xaMsn3
V5.1
V5.1
2dna1serugiF
01lbt1492
2941 drw 05
590
30pF
435
3.3V
DATAOUT
BUSY
INT
590
5pF*
435
3.3V
DATAOUT
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = V
IL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
51X50V07
ylnOl'moC
02X50V07
l'moC
dnI&
52X50V07
ylnOl'moC
tinUlobmySretemaraP.niM.xaM.niM.xaM.niM.xaM
ELCYCDAER
t
CR
emiTelcyCdaeR51
____
02
____
52
____
sn
t
AA
emiTsseccAsserddA
____
51
____
02
____
52sn
t
ECA
emiTsseccAelbanEpihC
)3(
____
51
____
02
____
52sn
t
EOA
emiTsseccAelbanEtuptuO
)3(
____
01
____
21
____
31sn
t
HO
egnahCsserddAmorfdloHtuptuO3
____
3
____
3
____
sn
t
ZL
emiTZ-woLtuptuO
)2,1(
3
____
3
____
3
____
sn
t
ZH
emiTZ-hgiHtuptuO
)2,1(
____
01
____
21
____
51sn
t
UP
emiTpUrewoPotelbanEpihC
)2,1(
0
____
0
____
0
____
sn
t
DP
emiTnwoDrewoPotelbasiDpihC
)2,1(
____
51
____
02
____
52sn
t
POS
(esluPetadpUgalFerohpameS EO ro MES )01
____
01
____
01
____
sn
t
AAS
sseccAsserddAerohpameS
)3(
____
51
____
02
____
52sn
a11lbt1492
53X50V07
ylnOl'moC
55X50V07
ylnOl'moC
tinUlobmySretemaraP.niM.xaM.niM.xaM
ELCYCDAER
t
CR
emiTelcyCdaeR 53
____
55
____
sn
t
AA
emiTsseccAsserddA
____
53
____
55sn
t
ECA
emiTsseccAelbanEpihC
)3(
____
53
____
55sn
t
EOA
emiTsseccAelbanEtuptuO
)3(
____
02
____
03sn
t
HO
egnahCsserddAmorfdloHtuptuO 3
____
3
____
sn
t
ZL
emiTZ-woLtuptuO
)2,1(
3
____
3
____
sn
t
ZH
emiTZ-hgiHtuptuO
)2,1(
____
51
____
52sn
t
UP
emiTpUrewoPotelbanEpihC
)2,1(
0
____
0
____
sn
t
DP
emiTnwoDrewoPotelbasiDpihC
)2,1(
____
53
____
05sn
t
POS
(esluPetadpUgalFerohpameS EO ro MES )51
____
51
____
sn
t
AAS
sseccAsserddAerohpameS
)3(
____
53
____
55sn
b11lbt1492
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
9
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
t
RC
R/W
CE
ADDR
t
AA
OE
2941 drw 07
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)

70V05L15J

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 8Kx8, 64K, 3.3V DUAL PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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