PL130-09SC Datasheet PL130-09SI, PL130-09SC, PL130-09SC-R | P1-P3

PL130-09

High Speed Translator Buffer to LVDS

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • t el +1(408) 944 -0800 • f ax +1(408) 474-1000 • www.mi crel.com Rev 1/5/12 Page 1

FEATURES

 Differential LVDS output

 Single AC coupled input (min. 100mV swing).

 Input range from 0 to 1.0GHz.

 2.5V to 3.3V operation.

 Available in 8-Pin SOP or 3x3mm QFN

GREEN/RoHS compliant packaging.

DESCRIPTION

The PL130-09 is a low cost, high performance,

high speed, buffer that reproduces any input fr e-

quency from 0 to 1.0GHz. It provides a pair of

differential LVDS output. Any input signal with at

least 100mV swing can be used as reference

signal. This chip is ideal for conversion from sine

wave, TTL, CMOS, or PECL to LVDS.

PIN CONFIGURATION

(TOP VIEW)

BLOCK DIAGRAM

Input

LVDS_BAR

REF_IN

LVDS

PL130-09

1

2

3

4 5

6

7

8

GND

REF_IN

GND

LVDS

VDD

LVDS_BAR

VDD

GND

LVDS_BAR

LVDS

GND

VDD

1 2 3 4

12 11 10 9

13

14

15

16

8

7

6

5

VDD

GND

VDD

GND

OE^

GND

REF_IN

GND

Note: ^ denotes internal pull up

PL130-09

High Speed Translator Buffer to LVDS

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • f ax +1(408) 474- 1000 • www.mi crel.com Rev 1/5 /12 Page 2

PIN DESCRIPTIONS

Name

Pin Number

Type

Description

SOP-8L

QFN-16L

GND

1,3,7

1,2,4,5,

9,13,14,15

P

Ground.

VDD

5,8

7,10,11,12

P

Power supply.

REF_IN

2

3

I

Reference input signal. The frequency of this signal will be re-

produced at the output (after translation to LVDS level).

LVDS

4

6

O

LVDS True output.

LVDS_BAR

6

8

O

LVDS Complementary output.

OE

N/A

16

I

Output enable (‘1’ for enable). Internal pull-up (default is ‘1’).

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

V

DD

4.6

V

Input Voltage, dc

V

I

-0.5

V

DD

+0.5

V

Output Voltage, dc

V

O

-0.5

V

DD

+0.5

V

Storage Temperature

T

S

-65

150

C

Ambient Operating Temperature*

T

A

-40

85

C

Junction Temperature

T

J

125

C

Lead Temperature (soldering, 10s)

260

C

ESD Protection, Human Body Model

2

kV

Expo sure of the device under co nditions beyond the limi ts specified by Ma ximum Ratings for e xtended perio ds may cause per mane nt damage to the

device and affect product reliability. These conditions represent a stress rat ing only , and fu nctional operati ons of the dev ice at these or any other co n-

ditions above t he operational l imits noted in this specifica tion is not implied. *Operating temperature is guaranteed by design. Parts are tested

to commercial grade only.

2. General Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current, No Load

I

DD

Fout = 200MHz, LVDS

25

30

mA

Operating Voltage

V

DD

2.25

3.63

V

Output Clock Duty Cycle

@ 1.25V (LVDS)

±5% of input

%

Short Circuit Current

50

mA

PL130-09

High Speed Translator Buffer to LVDS

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • f ax +1(408) 474- 1000 • www.mi crel.com Rev 1/5 /12 Page 3

3. AC Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Frequency

0

1000

MHz

Input signal swing

REF_IN input

100

mV

Output Frequency

0

1000

MHz

4. LVDS Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Output Differential Voltage

V

OD

R

L

= 100 

(see figure)

247

355

454

mV

V

DD

Magnitude Change

V

OD

-50

50

mV

Output High Voltage

V

OH

1.4

1.6

V

Output Low Voltage

V

OL

0.9

1.1

V

Offset Voltage

V

OS

1.125

1.2

1.375

V

Offset Magnitude Change

V

OS

0

3

25

mV

Power-off Leakage

I

OXD

V

ou t

= V

DD

or GND, V

DD

= 0V

1

10

uA

Output Short Circuit Current

I

OSD

-5.7

-8

mA

5. LVDS Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Differential Clock Rise Time

t

r

R

L

= 100 

C

L

= 10 pF

(see figure)

0.2

0.7

1.0

ns

Differential Clock Fall Time

t

f

0.2

0.7

1.0

ns

OUT

V

OD

V

OS

50?

OUT

V

DIFF

R

L

= 100?

C

L

= 10pF

C

L

= 10pF

LVDS Switching Test Circuit

LVDS Levels Test Circuit

LVDS Transistion Time Waveform

OUT

0V (Differential)

0V

20%

80%

20%

80%

t

R

t

F

V

DIFF

PL130-09SC

PL130-09SC

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