Micro Power 3 V Linear Hall Effect Sensor ICs
with Tri-State Output and User Selectable Sleep Mode
A1391, A1392,
A1393, and A1395
15
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Package EH, 6-pin MLP/DFN
C0.08
7X
C
SEATING
PLANE
6
21
A
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only, not for tooling use (reference DWG-2861;
reference JEDEC MO-229WCED, Type 1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
Reference land pattern layout;
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Hall Element (not to scale); U.S. customary dimensions controlling
Branding scale and appearance at supplier discretion
E
E
E
1
6
B
2
F
E
F
Active Area Depth, 0.32 mm NOM
1.00
3.70 1.25
0.50
0.95
0.30
1
6
G
G
PCB Layout Reference View
C
2.00 ±0.15
1.00
1.50
3.00 ±0.15
0.75 ±0.05
1.224 ±0.050
1.042
+0.100
–0.150
0.25 ±0.05
0.5 BSC
0.55 ±0.10
D
D
Coplanarity includes exposed thermal pad and terminals
Standard Branding Reference View
Y = Last two digits of year of manufacture
W = Week of manufacture
L = Lot number
N = Last two digits of device part number
YWW
LLL
NN
1
