P1817A/B
Low-Power Mobile VGA
EMI Reduction IC
©2010 SCILLC. All rights reserved. Pu
blication Order Number:
NOVEMBER 2010 – Rev. 2.1 P1817/D
Features
• FCC approved method of EMI attenuation.
•
Generates a low EMI spread spectrum clock of the
input frequency.
• Optimized for frequency range from:
P1817A – 20 to 32MHz
P1817B – 10 to 20MHz
• Internal loop filter minimizes external components
and board space.
• Two selectable spread ranges.
• Low inherent cycle-to-cycle jitter.
• 3.3V or 5V operating voltage range.
• TTL or CMOS compatible inputs and outputs.
• Ultra-low power CMOS design.
3.17mA @ 3.3V, 10MHz | 6.20mA @ 5.0V, 10MHz
4.28mA @ 3.3V, 14MHz | 7.50mA @ 5.0V, 14MHz
5.50mA @ 3.3V, 20MHz | 9.50mA @ 5.0V, 20MHz
• Supports notebook VGA and other LCD timing
controller applications.
• SSON / SBM pin for Spread Spectrum On/Off
and Standby Mode controls.
• Available in 8-pin SOIC package.
Pr
oduct Description
The P1817 is a versatile spread spectrum frequency
mo
dulator designed specifically for input clock
frequencies. The P1817 reduces electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of downstream clock and data
dependent signals. The P1817 allows significant system
cost savings by reducing the number of circuit board
layers, ferrite beads, shielding and other passive
components that are traditionally required to pass EMI
regulations.
The P1817 modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock, and
more importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
The P1817 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
Applications
The P1817 is targeted towards notebook LCD displays,
an
d other displays using an LVDS interface, PC
peripheral devices, and embedded systems.
Block Diagram
SR0
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
REF
XOUT
VSS
CLKIN / XIN
ModOUT
VDD
SSON
