74FST3257DTR2G

74FST3257
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4
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= −40_C to +85_C
Symbol Parameter Conditions (V) Min Typ* Max Units
V
IK
Clamp Diode Voltage I
IN
= −18 mA 4.5 −1.2 V
V
IH
High−Level Input Voltage 4.0 to 5.5 2.0 V
V
IL
Low−Level Input Voltage 4.0 to 5.5 0.8 V
I
I
Input Leakage Current 0 V
IN
5.5 V 5.5 ±1.0
mA
I
OZ
Off−State Leakage Current 0 A, B V
CC
5.5 ±1.0
mA
R
ON
Switch On Resistance (Note 6) V
IN
= 0 V, I
IN
= 64 mA 4.5 4 7
W
V
IN
= 0 V, I
IN
= 30 mA 4.5 4 7
V
IN
= 2.4 V, I
IN
= 15 mA 4.5 8 15
V
IN
= 2.4 V, I
IN
= 15 mA 4.0 11 20
I
CC
Quiescent Supply Current V
IN
= V
CC
or GND, I
OUT
= 0 5.5 3
mA
DI
CC
Increase In I
CC
per Input One input at 3.4 V,
Other inputs at V
CC
or GND
5.5 2.5 mA
*Typical values are at V
CC
= 5.0 V and T
A
= 25_C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
T
A
= −40_C to +85_C
C
L
= 50 pF, RU = RD = 500 W
V
CC
= 4.5−5.5 V V
CC
= 4.0 V
Symbol Parameter Conditions Min Max Min Max Units
t
PHL
,
t
PLH
Prop Delay Bus to Bus (Note 7)
V
I
= OPEN
0.25 0.25
ns
Prop Delay, Select to Bus A 1.0 4.7 5.2
t
PZH
,
t
PZL
Output Enable Time, Select to Bus B V
I
= 7 V for t
PZL
1.0 5.2 5.7
ns
Output Enable Time, I
OE
to Bus A, B V
I
= OPEN for t
PZH
1.0 5.1 5.6
t
PHZ
,
t
PLZ
Output Disable Time, Select to Bus B V
I
= 7 V for t
PLZ
1.0 5.2 5.5
ns
Output Disable Time, I
OE
to Bus A, B V
I
= OPEN for t
PHZ
1.0 5.5 5.5
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter Conditions Typ Max Units
C
IN
Control Pin Input Capacitance V
CC
= 5.0 V 3 pF
C
I/O
A Port Input/Output Capacitance V
CC
, OE = 5.0 V 7 pF
C
I/O
B Port Input/Output Capacitance V
CC
, OE = 5.0 V 5 pF
8. T
A
= )25_C, f = 1 MHz, Capacitance is characterized but not tested.
74FST3257
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5
V
I
V
OL
V
OL
+ 0.3 V
t
PLH
t
PLH
V
OL
V
OH
V
OH
− 0.3 V
t
PHZ
t
f
= 2.5 nS
90 %
1.5 V
10 %10 %
1.5 V
90 %
t
f
= 2.5 nS
t
PZL
t
PLZ
OUTPUT
1.5 V
OUTPUT
1.5 V
GND
3.0 V
t
PZH
ENABLE
INPUT
t
f
= 2.5 nS
90 %
1.5 V1.5 V
90 %
10 % 10 %
1.5 V 1.5 V
V
OH
GND
3.0 V
SWITCH
INPUT
t
f
= 2.5 nS
C
L
*
FROM
OUTPUT
UNDER
TEST
Figure 4. AC Test Circuit
Figure 5. Propagation Delays
AC Loading and Waveforms
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*C
L
= 50 pF
500 W
500 W
Figure 6. Enable/Disable Delays
OUTPUT
74FST3257
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6
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
6.40
16X
0.58
16X
1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B
S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____

74FST3257DTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers LOG QUAD 2:1 MULT
Lifecycle:
New from this manufacturer.
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