PM8324 TEMAP 84FDL
PMC-2052487, Issue 1
© Copyright PMC-Sierra, Inc. 2005
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.
High Density T1/E1 Framer with Integrated VT/TU
Mappers and M13 Muxes
Product Overview
The PM8324 TEMAP 84FDL is a high density T1/E1 framer with
integrated VT/TU mappers and M13 multiplexers. This feature-rich
device is ideally suited for applications performing high-density
transport or termination of channelized DS3 or unchannelized
DS3, E3, T1, or E1 over existing SONET/SDH facilities.
Product Highlights
• Processes 84 T1s/63 E1s or an STS-3/STM-1
• Integrates SONET/SDH and DS3/E3 functionality as well as 84
T1/63 E1 bidirectional PMON-capable transceivers:
• SONET/SDH functions include high order path processing, low
order path processing, T1/E1 to VT/TU mapping, and DS3/E3
to AU-3/TU-3 mapping
• DS3/E3 functions include three DS3/E3 bidirectional PMON-
capable transceivers and three M13 multiplexers
• Line side interfaces include:
• A 77.76 MHz byte wide parallel TelecomBus supporting an
STS-12/STM-4
• Two Working and two Protect 622 MHz serial TelecomBus
interfaces supporting a full STS-12/STM-4 of traffic
• Three serial DS3/E3/EC-1 links
• System side interface is a 19.44 MHz or 77.76 MHz byte serial SBI
TR bus used to connect T1/E1 line interface units
• Provides an input and output STS-1 level cross-connect to groom
incoming and outgoing data streams
• Provides a serial interface for extracting and inserting the low
order path and the high order path
• Supports bit asynchronous mapping of T1/E1 tributaries into
SONET/SDH
• Generates and terminates Low Order Path overhead (V5, J2, Z6,
Z7 bytes)
• Provides Full Duplex performance monitoring for T1, E1, DS3,
and E3 tributaries provided for add and drop directions
• Supports inband error reporting by updating the REI, RDI, and
auxiliary RDI bits in the V5 byte (G1 byte for TU-3) with the
status of the received tributary
• Supports M13 and C-bit parity DS3 formats
• Provides High Order Path overhead (J1, B3, C2, G1 bytes)
processing and the corresponding errors and indications
• Each T1 transceiver can be independently configured to support
the common DS1 signal formats (with full SF/ESF support or
partial SLC®96 support) or bypassed (unframed mode)
• Provides in-line DS3/E3 and T1/E1 framers and transmitters for
each data path allowing true bi-directional performance
monitoring of each path
• Each T1 transceiver:
• Detects the presence of Yellow and AIS patterns
• Integrates Yellow, Red, and AIS alarms
• Supports ingress performance monitoring, ESF bit-oriented
codes, HDLC messages on the ESF data link, inband loopback
codes, and PRBS generation/detection
STS-12/
STM-4
HO
POH
LO
POH
Term
S
P
E
&
T
R
I
B
U
T
A
R
Y
X
C
3x DS3/
E3
Framer
168x
T1/E1
Framer
168x
T1/E1
TRAN
3x DS3/
E3
TRAN
Mapper
3x DS3/
E3
TRAN
STS-1E
Line
Section
Gen
77MHz
Telecom Bus
3x
STS-1E
Clock and Data
3x
STS-1E
Clock and Data
3x DS3/E3 Clock and
Data
3x DS3/E3 Clock and Data
PMON/Alarms
STS-1/STM-0 and
VT/TU Loopback
PMON/Alarms
77 MHz
Telecom Bus
3x
M13/
G747
Mux
3x
M13/
G747
DeMux
PMON/Alarms
S
P
E
&
T
R
I
B
U
T
A
R
Y
X
C
PMON/Alarms
3x Unchannelized
DS3/E3
S
T
S
-
1
X
C
19.44 MHz or 77.76 MHz
SBI TR
W
P
W
P
W
P
W
P
622M
Interface
Main
19.44 MHz or 77.76 MHz SBI TR
STS-12/
STM-4
LO POH
HO POH
Gen
622M
Interface
Aux
622M
Interface
Main
STS-1E
Line
Section
Term
3x DS3/E3
Demapper
Framer
STS-3/
STM-1
VT/TU
Demapper
STS-3/
STM-1
VT/TU
Mapper
622M
Interface
Aux
S
T
S
-
1
X
C
Block Diagram
Released Product Brief
