15
As shown in Figure 18, 0.1 µF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
HCPL-7840. The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
HCPL-7840. A 0.01 µF bypass capacitor (C2) is also rec-
ommended at the input due to the switched-capacitor
also forms part of the anti-aliasing lter, which is recom-
mended to prevent high-frequency noise from aliasing
down to lower frequencies and interfering with the input
signal. The input lter also performs an important reliabil-
ity function—it reduces transient spikes from ESD events
owing through the current sensing resistor.
0.1 µF
+5 V
V
OUT
8
7
6
1
3
U2
5
2
4
R1
2.00 K
+15 V
C8
0.1 µF
0.1 µF
-15 V
–
+
MC34081
R3
10.0 K
HCPL-7840
C4
R4
10.0 K
C6
150 pF
U3
U1
78L05
IN OUT
C1
C2
0.01
µF
R5
68
GATE DRIVE
CIRCUIT
POSITIVE
FLOATING
SUPPLY
• • •
HV+
• • •
HV–
• • •
–+
R
SENSE
MOTOR
C5
150 pF
0.1
µF
0.1
µF
C3
C7
R2
2.00 K
Figure 18: Recommended application circuit.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away
from input signals, the use of ground and power planes,
etc. In addition, the layout of the PCB can also a ect the
isolation transient immunity (CMTI) of the HCPL-7840,
due primarily to stray capacitive coupling between the
input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the HCPL-7840.
Figure 19. Example printed circuit board layout.
C3
C2
C4
R5
TO R
SENSE+
TO R
SENSE–
TO V
DD1
TO V
DD2
V
OUT+
V
OUT–
