MAX1361EUB+T Datasheet MAX1361EUB+, MAX1362EUB+, MAX1361EUB+T | P10-P12

MAX1361/MAX1362

Power Supply

The MAX1361 (2.7V to 3.6V) and MAX1362 (4.5V to

5.5V) operate from a single supply and consume 670µA

(typ) at sampling rates up to 94.4ksps and 436µA in

monitor mode at 150ksps. The MAX1361 features a

2.048V internal reference and the MAX1362 features a

4.096V internal reference. All devices can be config-

ured for use with an external reference from 1V to V

Bypass V

to GND using a 0.1µF or greater ceramic

capacitor for best performance.

Analog Input and Track/Hold

The MAX1361/MAX1362 analog-input architecture con-

tains an analog-input multiplexer (MUX), fully differential

T/H, comparator, and a fully differential switched

capacitive digital-to-analog converter (DAC). Figure 3

shows the equivalent input circuit for the MAX1361/

MAX1362.

In single-ended mode, the analog-input MUX connects

T/H

between the analog input selected by CS[3:0] and

GND (see the

Configuration/Setup Bytes (Write Cycle)

section). In differential mode, the analog-input MUX

connects C

T/H

to the plus and minus analog inputs

selected by CS[3:0].

During the acquisition interval, the T/H switches are in

the track position, and C

T/H

charges to the analog-input

signal. At the end of the acquisition interval, the T/H

switches move to the hold position, retaining the charge

on C

T/H

as a stable sample of the input signal.

During the conversion, a switched capacitive DAC

adjusts to restore the comparator input voltage to 0V

within the limits of 10-bit resolution. This action requires

10 conversion clock cycles and is equivalent to trans-

ferring a charge of 11pF x (V

+ - V

-) from C

T/H

to the

binary-weighted capacitive DAC, forming a digital rep-

resentation of the analog-input signal.

Use a low source impedance to ensure an accurate

sample. A source impedance of up to 1.5kΩ does not

significantly degrade sampling accuracy. For larger

source impedances, connect a 100pF capacitor from

the analog input to GND or buffer the input.

In internal clock mode, the T/H circuitry enters track

mode on the eighth rising clock edge of the address

byte (see the

Slave Address

section). The T/H circuitry

enters hold mode on the falling clock edge of the

acknowledge bit of the address byte (the ninth clock

pulse). The conversions are then internally clocked, dur-

ing which time the MAX1361/MAX1362 hold SCL low.

In external clock mode, the T/H circuitry enters track

mode after a valid address on the rising edge of the

clock during the read bit (R/W = 1, bit 8). Hold mode is

entered on the rising edge of the second clock pulse

during the shifting out of the 1st byte of the result. The

next 10 clock cycles perform the conversions (see

Figure 13).

The time required for the T/H circuitry to acquire an

input signal is a function of the input sample capaci-

tance. If the analog-input source impedance is high,

the acquisition-time constant lengthens and more time

must be allowed between conversions. The acquisition

time (t

ACQ

) is the minimum time needed for the signal

to be acquired. It is calculated by:

ACQ

≥ 7 x (R

SOURCE

+ R

) x C

4-Channel, 10-Bit, System Monitor with Programmable

Trip Window and SMBus Alert Response

10 ______________________________________________________________________________________

TRACK

HOLD

T/H

TRACK

HOLD

AIN0

AIN1

AIN2

AIN3/REF

ANALOG INPUT MUX

CAPACITIVE

DAC

REF

CAPACITIVE

DAC

REF

MAX1361

MAX1362

HOLD

TRACK

HOLD

Figure 3. Equivalent Input Circuit

where R

SOURCE

is the analog-input source impedance,

= 2.5kΩ, and C

= 22pF. For internal clock mode,

ACQ

= 1.5/f

SCL

, and for external clock mode t

ACQ

2/f

SCL

Analog-Input Bandwidth

The MAX1361/MAX1362 feature input-tracking circuitry

with a 5MHz small-signal bandwidth. The 5MHz input

bandwidth makes it possible to digitize high-speed

transient events and measure periodic signals with

bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid high-fre-

quency signals from aliasing into the frequency band of

interest, use anti-aliasing filtering.

Analog-Input Range and Protection

Internal protection diodes clamp the analog inputs to V

and GND. These diodes allow the analog inputs to swing

from (V

GND

- 0.3V) to (V

+ 0.3V) without causing dam-

age to the device. For accurate conversions the inputs

must remain within 50mV below GND or above V

Single-Ended/Differential Input

The SE/DIF of the configuration byte configures the

MAX1361/MAX1362 analog-input circuitry for single-

ended or differential input. In single-ended mode (SE/DIF

= 1), the digital conversion results are the difference

between the analog input selected by CS[3:0] and GND.

In differential mode (SE/DIF = 0), the digital conversion

results are the difference between the plus and the minus

analog inputs selected by CS[3:0] (see Tables 5 and 6).

Unipolar/Bipolar

Unipolar mode sets the differential input range from 0 to

REF

. A negative differential analog input in unipolar

mode causes the digital output code to be zero.

Selecting bipolar mode sets the differential input range

to ±V

REF

/2. The digital output code is binary in unipolar

mode and two’s complement in bipolar mode. (See the

Transfer Functions

section.)

In single-ended mode the MAX1361/MAX1362 always

operate in unipolar mode. The analog inputs are inter-

nally referenced to GND with a full-scale input range

from 0 to V

REF

(Table 7).

Reference

SEL[1:0] of the setup byte controls the reference and

the AIN3/REF configuration. When AIN3/REF is config-

ured as a reference input or reference output (SEL0 =

1), differential conversions on AIN3/REF appear as if

AIN3/REF is connected to GND. A single-ended conver-

sion in scan mode on AIN3/REF is ignored by an internal

limiter that sets the highest available channel at AIN2

(Table 2).

Internal Reference

The internal reference is 2.048V for the MAX1361 and

4.096V for the MAX1362. SEL0 of the setup byte con-

trols whether AIN3/REF is used for an analog input or a

reference (SEL0 = 0 selects AIN3/REF as AIN3, and

SEL0 = 1 selects AIN3/REF as REF). Decouple

AIN3/REF to GND with a 0.1µF capacitor and a 2kΩ

resistor in series when AIN3/REF is configured as an

internal reference output (SEL[1:0] = 11). See the

Typical Operating Circuit.

Once powered up, the refer-

ence remains on until reconfigured. Do not use the ref-

erence to supply current for external circuitry.

External Reference

The external reference ranges from 1V to V

. For max-

imum conversion accuracy, the reference must deliver

40µA and have an impedance of 500Ω or less. For

noisy or high-output-impedance references, insert a

0.1µF bypass capacitor to GND as close to AIN3/REF

as possible.

Clock Modes

The clock mode determines the conversion clock and

the data acquisition and conversion time. The clock

mode also affects the scan mode. The state of the

setup byte’s INT/EXT clock bit determines the clock

mode. At power-up, the MAX1361/MAX1362 default to

internal clock mode (INT/EXT clock = 0).

Internal Clock

See the

Configuration/Setup Bytes (Write Cycle)

section.

In internal clock mode (INT/EXT clock = 0), the MAX1361/

MAX1362 use an internal oscillator for the conversion

clock. The MAX1361/MAX1362 begin tracking the analog

input after a valid address on the eighth rising edge of the

clock. On the falling edge of the ninth clock, the analog

signal is acquired and the conversion begins. While con-

verting, the MAX1361/MAX1362 hold SCL low (clock

stretching). After completing the conversion, the results

are stored in internal memory. For scan-mode configura-

tions with multiple conversions (see the

Scan Modes

sec-

tion), all conversions happen in succession with each

additional result stored in memory. Once all conversions

are complete, the MAX1361/MAX1362 release SCL,

allowing it to go high. The master can now clock the

results out in the same order as the scan conversion.

The converted results are read back in a FIFO

sequence. If AIN3/REF is configured as a reference

input or output, AIN3/REF is excluded from multichan-

nel scan. If reading continues past the final result

stored in memory, the pointer wraps around and points

to the first result. Only the current conversion results

are read from memory. The MAX1361/MAX1362 must

MAX1361/MAX1362

4-Channel, 10-Bit, System Monitor with Programmable

Trip Window and SMBus Alert Response

______________________________________________________________________________________ 11

MAX1361/MAX1362

be addressed with a read command to obtain new con-

version results.

External Clock

See the

Configuration/Setup Bytes (Write Cycle)

section.

When configured for external clock mode (INT/EXT = 1),

the MAX1361/MAX1362 use SCL as the conversion clock.

In external clock mode, the MAX1361/MAX1362 begin

tracking the analog input on the eighth rising clock edge

of a valid slave address byte. Two SCL clock cycles later,

the analog signal is acquired and the conversion begins.

Unlike internal clock mode, converted data is clocked out

immediately in the format described in the

Reading a

Conversion (Read Cycle)

section.

The device continuously converts input channels dictat-

ed by the scan mode until given a not acknowledge

(NACK). There is no need to readdress the device with

a read command to obtain new conversion results.

The conversion must complete in 1ms or droop on the

T/H capacitor degrades conversion results. Use internal

clock mode if the SCL clock period exceeds 60µs.

Use external clock mode for conversion rates from

40ksps to 94.4ksps. Use internal clock mode for con-

versions under 40ksps. Internal clock mode consumes

less power. Monitor mode always uses internal clock

mode regardless of conversion rate.

Applications Section

Power-On Reset

The configuration and setup registers default to a sin-

gle-ended, unipolar, single-channel conversion on AIN0

using the internal clock with V

as the reference and

AIN3/REF configured as an analog input. The memory

contents are unknown at power-up (see the

Software

Description

section).

C-Compatible 2-Wire Serial Interface

The MAX1361/MAX1362 use an I

C-compatible 2-wire

interface consisting of a serial-data line (SDA) and seri-

al-clock line (SCL). SDA and SCL facilitate bidirectional

communication between the MAX1361/MAX1362 and

the master at rates up to 1.7MHz. The master (typically

a microcontroller) initiates data transfer on the bus and

generates the SCL signal to permit data transfer. The

MAX1361/MAX1362 behave as I

C slave devices that

transfer and receive data.

SDA and SCL must be pulled high for proper I

C opera-

tion. This is typically done with pullup resistors (750Ω or

greater). Series resistors (R

) are optional (see the

Typical Operating Circuit

section). The resistors protect

the input architecture of the MAX1361/MAX1362 from

high voltage spikes on the bus lines and minimize

crosstalk and undershoot of the bus signals.

One bit transfers during each SCL clock cycle. A mini-

mum of nine clock cycles is required to transfer a byte

in or out of the MAX1361/MAX1362 (8 bits and an

ACK/NACK). The data on SDA must remain stable dur-

ing the high period of the SCL clock pulse. Changes in

SDA while SCL is high and stable are considered con-

trol signals (see the

START and STOP Conditions

sec-

tion). Both SDA and SCL remain high when the bus is

not busy.

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), which is a high-to-low transition on SDA while

SCL is high. The master terminates a transmission with

a STOP condition (P), which is a low-to-high transition

on SDA while SCL is high (Figure 4). A repeated START

condition (Sr) can be used in place of a STOP condition

to leave the bus active and the mode unchanged (see

the

HS I

C Mode

section).

Acknowledge and Not-Acknowledge Conditions

Data transfers are framed with an acknowledge bit

(ACK) or a not-acknowledge bit (NACK). Both the mas-

ter and the MAX1361/MAX1362 (slave) generate

acknowledge bits. To generate an acknowledge, the

receiving device must pull SDA low before the rising

edge of the acknowledge-related clock pulse (ninth

pulse) and keep it low during the high period of the

clock pulse (Figure 5).

4-Channel, 10-Bit, System Monitor with Programmable

Trip Window and SMBus Alert Response

12 ______________________________________________________________________________________

SCL

SDA

Figure 4. START and STOP Conditions

SCL

SDA

NOT ACKNOWLEDGE

ACKNOWLEDGE

12 89

Figure 5. Acknowledge Bits

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MAX1361EUB+T

Mfr. #:

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Analog to Digital Converters - ADC 10-Bit 4Ch 150ksps 3.6V Precision ADC

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