www.fairchildsemi.com 2
74F899
Input Loading/Fan-Out
Pin Descriptions
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
• Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL
) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB
(ERRA).
• Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL
is HIGH. Parity is still generated and
checked as ERRA
and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
• Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
HIGH/LOW
Pin Names Description U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A
0
–A
7
Data Inputs/ 1.0/1.0 20 µA/−0.6 mA
Data Outputs 150/40 −3 mA/24 mA
B
0
–B
7
Data Inputs/ 1.0/1.0 20 µA/−0.6 mA
Data Outputs 600/106.6 −12 mA/64 mA
APAR A Bus Parity 1.0/1.0 20 µA/−0.6 mA
Input/Output 150/40 −3 mA/24 mA
BPAR B Bus Parity 1.0/1.0 20 µA/−0.6 mA
Input/Output 600/106.6 −12 mA/64 mA
ODD/EVEN
Parity Select Input 1.0/1.0 20 µA/−0.6 mA
GBA
, GAB
Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA
SEL
Mode Select Input 1.0/1.0 20 µA/−0.6 mA
LEA, LEB Latch Enable Inputs 1.0/1.0 20 µA/−0.6 mA
ERRA
, ERRB
Error Signal Outputs 50/33.3 −1 mA/20 mA
Pin Names Description
A
0
–A
7
A Bus Data Inputs/Data Outputs
B
0
–B
7
B Bus Data Inputs/Data Outputs
APAR, BPAR A and B Bus Parity Inputs
ODD/EVEN
ODD/EVEN Parity Select, Active LOW for EVEN Parity
GBA
, GAB Output Enables for A or B Bus, Active LOW
SEL
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode
ERRA
, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
