74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 13 of 21
NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8
.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
(1) CE
may change only from HIGH-to-LOW while CP is LOW, see Section 1.
Fig 10. Waveforms showing set-up and hold times
t
h
t
su
t
su
t
h
t
W
V
M
V
M
GND
V
I
GND
V
I
DS input
t
su
V
M
mna990
GND
V
I
CP, CE input
CP, CE input
(1)
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
mna991
Dn input
PL input
t
su
t
h
V
I
GND
V
I
GND
V
M
V
M
t
su
t
h
V
M
V
M
Table 8. Measurement points
Type Input Output
V
I
V
M
V
M
74HC165-Q100 V
CC
0.5V
CC
0.5V
CC
74HCT165-Q100 3 V 1.3 V 1.3 V
