© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 10
1 Publication Order Number:
MC10E136/D
MC10E136, MC100E136
5 V ECL 6‐Bit Universal
Up/Down Counter
Description
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. The device generates a look-ahead-carry
output and accepts a look-ahead-carry input. These two features allow
for the cascading of multiple E136’s for wider bit width counters that
operate at very nearly the same frequency as the stand alone counter.
The CLOUT
output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT
output will pulse
LOW for one clock cycle when the counter reaches terminal count.
For more information on utilizing the look-ahead-carry features of the
device please refer to the applications section of this data sheet. The
differential COUT output facilitates the E136’s use in programmable
divider and self-stopping counter applications.
Unlike the H136 and other similar universal counter designs, the E136
carry-out and look-ahead-carry-out signals are registered on chip.
This design alleviates the glitch problem seen on many counters
where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the
E136 and H136 counters. The user, regardless of familiarity with the
H136, should read this data sheet carefully. Note specifically (see
logic diagram) the operation of the carry out outputs and the
look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input
pull-down resistor. The master reset is an asynchronous signal which
when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function
properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left
open. This practice will minimize switching noise which can reduce
the maximum count frequency of the device or significantly reduce
margins against other noise in the system.
Features
• 550 MHz Count Frequency
• Fully Synchronous Up and Down Counting
• Look-Ahead-Carry Input and Output
• Asynchronous Master Reset
• PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
> 2 kV Human Body Model
> 200 V Machine Model
• Meets or Exceeds JEDEC Standard EIA/JESD78,
IC Latchup Test
MARKING DIAGRAM*
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
PLCC−28
FN SUFFIX
CASE 776−02
MCxxxE136G
AWLYYWW
1
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Applicati
Note AND8003/D)
• Flammability Rating: UL 94 V−0
@ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 506 Devices
• These Devices are Pb-Free, Halogen Free
and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information on page 10
of this data sheet.
